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Freescale Semiconductor Data Sheet: Technical Data
Document Number: DSP56367 Rev. 2.1, 1/2007
DSP56367
24-Bit Audio Digital Signal Processor
1
Overview
Contents
1 2 3 4 5 A Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal/Connection Descriptions . . . . . . . . . . . Specifications . . . . . . . . . . . . . . . . . . . . . . . . . Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . . . . . Power Consumption Benchmark . . . . . . . . . . 1-1 2-1 3-1 4-1 5-1 A-1
This document briefly describes the DSP56367 24-bit digital signal processor (DSP). The DSP56367 is a member of the DSP56300 family of programmable CMOS DSPs. The DSP56367 is targeted to applications that require digital audio compression/decompression, sound field processing, acoustic equalization and other digital audio algorithms. The DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.5 V.
This document contains information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved.
Overview
Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage* VIL / VOL VIH / VOH VIH / VOH VIL / VOL
Note:*Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
1 2 16 8 4 6 5 MEMORY EXPANSION AREA TRIPLE TIMER
DAX (SPDIF Tx.) INTERFACE PROGRAM RAM /INSTR. CACHE 3K x 24 PROGRAM ROM 40K x 24 Bootstrap ROM 192 x 24
HOST INTERFACE
ESAI INTERFACE ESAI_1
SHI INTERFACE
X MEMORY RAM 13K X 24 ROM 32K x 24 XM_EB
Y MEMORY RAM 7K X 24 ROM 8K x 24 YM_EB
EXTERNAL ADDRESS BUS SWITCH DRAM & SRAM BUS INTERFACE & I - CACHE
PIO_EB
PERIPHERAL EXPANSION AREA
ADDRESS GENERATION UNIT SIX CHANNELS DMA UNIT
PM_EB
YAB XAB PAB DAB
18 ADDRESS
24-BIT DSP56300 Core DDB YDB
INTERNAL DATA BUS SWITCH
10 CONTROL
XDB PDB GDB
EXTERNAL DATA BUS SWITCH
24 DATA
POWER MNGMNT
PLL
CLOCK GENERATOR
PROGRAM INTERRUPT CONTROLLER PROGRAM DECODE CONTROLLE PROGRAM ADDRESS GENERATOR
DATA ALU 24X24+56->56-BIT MAC TWO 56-BIT ACCUMULATORS BARREL SHIFTER
JTAG OnCETM
4
EXTAL RESET PINIT/NMI
MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD
24 BITS BUS
Figure 1-1 DSP56367 Block Diagram
DSP56367 Technical Data, Rev. 2.1 1-2 Freescale Semiconductor
Overview
1.1
Features
Core features are described fully in the DSP56300 Family Manual.
1.2
* * * * * * * * * * *
DSP56300 modular chassis
150 Million Instructions Per Second (MIPS) with a 150 MHz clock at internal logic supply (QVCCL) of 1.8V. 100 Million Instructions Per Second (MIPS) with a 100 MHz clock at internal logic supply (QVCCL) of 1.5V. Object Code Compatible with the 56K core. Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support. Program Control with position independent code support and instruction cache support. Six-channel DMA controller. PLL based clocking with a wide range of frequency multiplications (1 to 4096), predivider factors (1 to 16) and power saving clock divider (2i: i=0 to 7). Reduces clock noise. Internal address tracing support and OnCETM for Hardware/Software debugging. JTAG port. Very low-power CMOS design, fully static design with operating frequencies down to DC. STOP and WAIT low-power standby modes.
1.3
* * * * *
On-chip Memory Configuration
7K x 24 Bit Y-Data RAM and 8K x 24 Bit Y-Data ROM. 13K x 24 Bit X-Data RAM and 32K x 24 Bit X-Data ROM. 40K x 24 Bit Program ROM. 3K x 24 Bit Program RAM and 192x24 Bit Bootstrap ROM. 1K of Program RAM may be used as Instruction Cache or for Program ROM patching. 2K x 24 Bit from Y Data RAM and 5K x 24 Bit from X Data RAM can be switched to Program RAM resulting in up to 10K x 24 Bit of Program RAM.
1.4
* * * *
Off-chip memory expansion
External Memory Expansion Port. Off-chip expansion up to two 16M x 24-bit word of Data memory. Off-chip expansion up to 16M x 24-bit word of Program memory. Simultaneous glueless interface to SRAM and DRAM.
1.5
*
Peripheral modules
Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols.
DSP56367 Technical Data, Rev. 2.1
Freescale Semiconductor
1-3
Overview
*
* * * * *
Serial Audio Interface I(ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks) Serial Host Interface (SHI): SPI and I2C protocols, multi master capability, 10-word receive FIFO, support for 8, 16 and 24-bit words. Byte-wide parallel Host Interface (HDI08) with DMA support. Triple Timer module (TEC). Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU digital audio formats. Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
1.6 1.7
144-pin plastic LQFP package Documentation
Table 1-1 lists the documents that provide a complete description of the DSP56367 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). Table 1-1 DSP56367 Documentation
Document Name DSP56300 Family Manual DSP56367 Product Brief DSP56367 User's Manual DSP56367 Technical Data Sheet (this document) IBIS Model Description Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Brief description of the chip DSP56367 User's Manual Electrical and timing specifications; pin and package descriptions Input Output Buffer Information Specification Order Number DSP56300FM DSP56367P DSP56367UM DSP56367 For software or simulation models, contact sales or go to www.freescale.com.
DSP56367 Technical Data, Rev. 2.1 1-4 Freescale Semiconductor
2
2.1
Signal/Connection Descriptions
Signal Groupings
The input and output signals of the DSP56367 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure 2-1. The DSP56367 is operated from a 1.8V supply; however, some of the inputs can tolerate 3.3V. A special notice for this feature is added to the signal descriptions of those inputs. Remember, the DSP56367 offers 150 million instructions per second (MIPS) using an internal 150 MHz clock at 1.8 V and 100 million instructions per second (MIPS) using an internal 100 MHz clock at 1.3.3V.
Table 2-1 DSP56367 Functional Signal Groupings
Functional Group Power (VCC) Ground (GND) Clock and PLL Address bus Data bus Bus control Interrupt and mode control HDI08 SHI ESAI ESAI_1 Digital audio transmitter (DAX) Timer JTAG/OnCE Port
1 2
Number of Signals 20 18 3 18 Port A
1
Detailed Description
Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-14 Table 2-15
24 10 5
Port B2
16 5
Port C3 Port E4 Port D5
12 6 2 1 4
Port A is the external memory interface port, including the external address bus, data bus, and control signals. Port B signals are the GPIO port signals which are multiplexed with the HDI08 signals. 3 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 4 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 5 Port D signals are the GPIO port signals which are multiplexed with the DAX signals.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-1
Signal Groupings
PORT A ADDRESS BUS A0-A17 VCCA (3) GNDA (4) PORT A DATA BUS D0-D23 VCCD (4) GNDD (4) PORT A BUS CONTROL AA0-AA2/RAS0-RAS2 CAS RD WR TA BR BG BB VCCC (2) GNDC (2) INTERRUPT AND MODE CONTROL MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD RESET PLL AND CLOCK EXTAL PINIT/NMI PCAP VCCP GNDP QUIET POWER VCCQH (3) VCCQL (4) GNDQ (4) SPDIF TRANSMITTER (DAX) ADO [PD1] ACI [PD0] TIMER 0 TIO0 [TIO0] Port D Port E Port C Port B DSP56367
OnCE ON-CHIP EMULATION/ JTAG PORT TDI TCK TDO TMS PARALLEL HOST PORT (HDI08) HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] HRW/HRD [PB11] HDS/HWR [PB12] HCS/HA10 [PB13] HOREQ/HTRQ [PB14] HACK/HRRQ [PB15] VCCH GNDH SERIAL AUDIO INTERFACE (ESAI) SCKT[PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] SERIAL AUDIO INTERFACE(ESAI_1) SCKT_1[PE3] FS T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2) SERIAL HOST INTERFACE (SHI) MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ
Figure 2-1 Signals Identified by Functional Group
DSP56367 Technical Data, Rev. 2.1 2-2 Freescale Semiconductor
Power
2.2
Power
Table 2-2 Power Inputs
Description PLL Power--VCCP is VCC dedicated for PLL use. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. There is one VCCP input. Quiet Core (Low) Power--VCCQL is an isolated power for the internal processing logic. This input must be tied externally to all other VCCQL power pins and the VCCP power pin only. Do not tie with other power pins. The user must provide adequate external decoupling capacitors. There are four VCCQL inputs. Quiet External (High) Power--VCCQH is a quiet power source for I/O lines. This input must be tied externally to all other chip power inputs.The user must provide adequate decoupling capacitors. There are three VCCQH inputs. Address Bus Power--VCCA is an isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are three VCCA inputs. Data Bus Power--VCCD is an isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are four VCCD inputs. Bus Control Power--VCCC is an isolated power for the bus control I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCC inputs. Host Power--VCCH is an isolated power for the HDI08 I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There is one VCCH input. SHI, ESAI, ESAI_1, DAX and Timer Power --VCCS is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. There are two VCCS inputs.
Power Name VCCP VCCQL (4)
VCCQH (3)
VCCA (3)
VCCD (4)
VCCC (2)
VCCH
VCCS (2)
2.3
Ground
Table 2-3 Grounds
Description PLL Ground--GNDP is a ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. There is one GNDP connection. Quiet Ground--GNDQ is an isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDQ connections. Address Bus Ground--GNDA is an isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDA connections. Data Bus Ground--GNDD is an isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GNDD connections. DSP56367 Technical Data, Rev. 2.1
Ground Name GNDP
GNDQ (4)
GNDA (4)
GNDD (4)
Freescale Semiconductor
2-3
Clock and PLL
Table 2-3 Grounds (continued)
Ground Name GNDC (2) Description Bus Control Ground--GNDC is an isolated ground for the bus control I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDC connections. Host Ground--GNDh is an isolated ground for the HD08 I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There is one GNDH connection. SHI, ESAI, ESAI_1, DAX and Timer Ground--GNDS is an isolated ground for the SHI, ESAI, ESAI_1, DAX and Timer. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are two GNDS connections.
GNDH
GNDS (2)
2.4
Clock and PLL
Table 2-4 Clock and PLL Signals
Type Input State During Reset Input Signal Description External Clock Input--An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL. PLL Capacitor--PCAP is an input connecting an off-chip capacitor to the PLL filter. Connect one capacitor terminal to PCAP and the other terminal to VCCP. If the PLL is not used, PCAP may be tied to VCC, GND, or left floating.
Signal Name EXTAL
PCAP
Input
Input
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt--During assertion of RESET, the value of PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register, determining whether the PLL is enabled or disabled. After RESET de assertion and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered nonmaskable interrupt (NMI) request internally synchronized to internal system clock.
2.5
External Memory Expansion Port (Port A)
When the DSP56367 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0-A17, D0-D23, AA0/RAS0-AA2/RAS2, RD, WR, BB, CAS.
2.6
External Address Bus
Table 2-5 External Address Bus Signals
State During Reset Tri-Stated
Signal Name A0-A17
Type Output
Signal Description Address Bus--When the DSP is the bus master, A0-A17 are active-high outputs that specify the address for external program and data memory accesses. Otherwise, the signals are tri-stated. To minimize power dissipation, A0-A17 do not change state when external memory spaces are not being accessed.
DSP56367 Technical Data, Rev. 2.1 2-4 Freescale Semiconductor
External Data Bus
2.7
External Data Bus
Table 2-6 External Data Bus Signals
State during Reset Tri-Stated
Signal Name D0-D23
Type Input/Output
Signal Description Data Bus--When the DSP is the bus master, D0-D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0-D23 are tri-stated.
2.8
External Bus Control
Table 2-7 External Bus Control Signals
State During Reset Tri-Stated
Signal Name AA0-AA2/ RAS0-RAS2
Type Output
Signal Description Address Attribute or Row Address Strobe--When defined as AA, these signals can be used as chip selects or additional address lines. When defined as RAS, these signals can be used as RAS for DRAM interface. These signals are tri-statable outputs with programmable polarity. Column Address Strobe-- When the DSP is the bus master, CAS is an active-low output used by DRAM to strobe the column address. Otherwise, if the bus mastership enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated. Read Enable--When the DSP is the bus master, RD is an active-low output that is asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tri-stated. Write Enable--When the DSP is the bus master, WR is an active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-stated.
CAS
Output
Tri-Stated
RD
Output
Tri-Stated
WR
Output
Tri-Stated
TA
Input
Ignored Input Transfer Acknowledge--If the DSP is the bus master and there is no external bus activity, or the DSP is not the bus master, the TA input is ignored. The TA input is a data transfer acknowledge (DTACK) function that can extend an external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait states inserted by the BCR by keeping TA deasserted. In typical operation, TA is deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle, and is deasserted before the next bus cycle. The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock. The number of wait states is determined by the TA input or by the bus control register (BCR), whichever is longer. The BCR can be used to set the minimum number of wait states in external bus cycles. In order to use the TA functionality, the BCR must be programmed to at least one wait state. A zero wait state access cannot be extended by TA deassertion, otherwise improper operation may result. TA can operate synchronously or asynchronously, depending on the setting of the TAS bit in the operating mode register (OMR). TA functionality may not be used while performing DRAM type accesses, otherwise improper operation may result.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-5
Interrupt and Mode Control
Table 2-7 External Bus Control Signals (continued)
Signal Name BR Type Output State During Reset Signal Description
Output Bus Request--BR is an active-low output, never tri-stated. BR is asserted when the (deasserted) DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56367 is a bus master or a bus slave. Bus "parking" allows BR to be deasserted even though the DSP56367 is the bus master. (See the description of bus "parking" in the BB signal description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus. BR is typically sent to an external bus arbitrator that controls the priority, parking, and tenure of each master on the same external bus. BR is only affected by DSP requests for the external bus, never for the internal bus. During hardware reset, BR is deasserted and the arbitration is reset to the bus slave state. Ignored Input Bus Grant--BG is an active-low input. BG is asserted by an external bus arbitration circuit when the DSP56367 becomes the next bus master. When BG is asserted, the DSP56367 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution. For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set.
BG
Input
BB
Input/ Output
Input
Bus Busy--BB is a bidirectional active-low input/output. BB indicates that the bus is active. Only after BB is deasserted can the pending bus master become the bus master (and then assert the signal again). The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted. This is called "bus parking" and allows the current bus master to reuse the bus without rearbitration until another device requires the bus. The deassertion of BB is done by an "active pull-up" method (i.e., BB is driven high and then released and held high by an external pull-up resistor). For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set. BB requires an external pull-up resistor.
2.9
Interrupt and Mode Control
The interrupt and mode control signals select the chip's operating mode as it comes out of hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.
DSP56367 Technical Data, Rev. 2.1 2-6 Freescale Semiconductor
Interrupt and Mode Control
Table 2-8 Interrupt and Mode Control
Signal Name MODA/IRQA Type Input State During Reset Input Signal Description Mode Select A/External Interrupt Request A--MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into the OMR when the RESET signal is deasserted. If the processor is in the stop standby state and the MODA/IRQA pin is pulled to GND, the processor will exit the stop state. This input is 3.3V tolerant. MODB/IRQB Input Input Mode Select B/External Interrupt Request B--MODB/IRQB is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant. MODC/IRQC Input Input Mode Select C/External Interrupt Request C--MODC/IRQC is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant. MODD/IRQD Input Input Mode Select D/External Interrupt Request D--MODD/IRQD is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing. MODA, MODB, MODC, and MODD select one of 16 initial chip operating modes, latched into OMR when the RESET signal is deasserted. This input is 3.3V tolerant. RESET Input Input Reset--RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input is 3.3V tolerant.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-7
Parallel Host Interface (HDI08)
2.10
Parallel Host Interface (HDI08)
The HDI08 provides a fast, 8-bit, parallel data port that may be connected directly to the host bus. The HDI08 supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers, microprocessors, DSPs, and DMA hardware.
Table 2-9 Host Interface
Signal Name H0-H7 Type Input/ Output Input/ Output Input, Output, or Disconnected State During Reset Signal Description
GPIO Host Data--When HDI08 is programmed to interface a nonmultiplexed host Disconnected bus and the HI function is selected, these signals are lines 0-7 of the bidirectional, tri-state data bus. Host Address/Data--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, these signals are lines 0-7 of the address/data bidirectional, multiplexed, tri-state bus. Port B 0-7--When the HDI08 is configured as GPIO, these signals are individually programmable as input, output, or internally disconnected. The default state after reset for these signals is GPIO disconnected. These inputs are 3.3V tolerant.
HAD0-HAD7
PB0-PB7
HA0
Input
GPIO Host Address Input 0--When the HDI08 is programmed to interface a Disconnected nonmultiplexed host bus and the HI function is selected, this signal is line 0 of the host address input bus. Host Address Strobe--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is the host address strobe (HAS) Schmitt-trigger input. The polarity of the address strobe is programmable, but is configured active-low (HAS) following reset. Port B 8--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HAS/HAS
Input
PB8
Input, Output, or Disconnected
HA1
Input
GPIO Host Address Input 1--When the HDI08 is programmed to interface a Disconnected nonmultiplexed host bus and the HI function is selected, this signal is line 1 of the host address (HA1) input bus. Host Address 8--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 8 of the host address (HA8) input bus. Port B 9--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HA8
Input
PB9
Input, Output, or Disconnected
DSP56367 Technical Data, Rev. 2.1 2-8 Freescale Semiconductor
Parallel Host Interface (HDI08)
Table 2-9 Host Interface (continued)
Signal Name HA2 Type Input State During Reset Signal Description
GPIO Host Address Input 2--When the HDI08 is programmed to interface a Disconnected non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. Host Address 9--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 9 of the host address (HA9) input bus. Port B 10--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HA9
Input
PB10
Input, Output, or Disconnected
HRW
Input
GPIO Host Read/Write--When HDI08 is programmed to interface a Disconnected single-data-strobe host bus and the HI function is selected, this signal is the Host Read/Write (HRW) input. Host Read Data--When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host read data strobe (HRD) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HRD) after reset. Port B 11--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HRD/ HRD
Input
PB11
Input, Output, or Disconnected
HDS/ HDS
Input
GPIO Host Data Strobe--When HDI08 is programmed to interface a Disconnected single-data-strobe host bus and the HI function is selected, this signal is the host data strobe (HDS) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HDS) following reset. Host Write Data--When HDI08 is programmed to interface a double-data-strobe host bus and the HI function is selected, this signal is the host write data strobe (HWR) Schmitt-trigger input. The polarity of the data strobe is programmable, but is configured as active-low (HWR) following reset. Port B 12--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HWR/ HWR
Input
PB12
Input, Output, or Disconnected
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-9
Parallel Host Interface (HDI08)
Table 2-9 Host Interface (continued)
Signal Name HCS Type Input State During Reset Signal Description
GPIO Host Chip Select--When HDI08 is programmed to interface a Disconnected nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. Host Address 10--When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected, this signal is line 10 of the host address (HA10) input bus. Port B 13--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HA10
Input
PB13
Input, Output, or Disconnected
HOREQ/ HOREQ
Output
GPIO Host Request--When HDI08 is programmed to interface a single host Disconnected request host bus and the HI function is selected, this signal is the host request (HOREQ) output. The polarity of the host request is programmable, but is configured as active-low (HOREQ) following reset. The host request may be programmed as a driven or open-drain output. Transmit Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the transmit host request (HTRQ) output. The polarity of the host request is programmable, but is configured as active-low (HTRQ) following reset. The host request may be programmed as a driven or open-drain output. Port B 14--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HTRQ/ HTRQ
Output
PB14
Input, Output, or Disconnected
HACK/ HACK
Input
GPIO Host Acknowledge--When HDI08 is programmed to interface a single host Disconnected request host bus and the HI function is selected, this signal is the host acknowledge (HACK) Schmitt-trigger input. The polarity of the host acknowledge is programmable, but is configured as active-low (HACK) after reset. Receive Host Request--When HDI08 is programmed to interface a double host request host bus and the HI function is selected, this signal is the receive host request (HRRQ) output. The polarity of the host request is programmable, but is configured as active-low (HRRQ) after reset. The host request may be programmed as a driven or open-drain output. Port B 15--When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant.
HRRQ/ HRRQ
Output
PB15
Input, Output, or Disconnected
DSP56367 Technical Data, Rev. 2.1 2-10 Freescale Semiconductor
Serial Host Interface
2.11
Serial Host Interface
Table 2-10 Serial Host Interface Signals
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Signal Name SCK
Signal Type Input or Output
State During Reset Tri-Stated
Signal Description SPI Serial Clock--The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the slave select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock--SCL carries the clock for I2C bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant.
SCL
Input or Output
MISO
Input or Output
Tri-Stated
SPI Master-In-Slave-Out--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. An external pull-up resistor is not required for SPI operation. I2C Data and Acknowledge--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of start and stop events. A high-to-low transition of the SDA line while SCL is high is a unique situation, and is defined as the start event. A low-to-high transition of SDA while SCL is high is a unique situation defined as the stop event. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant.
SDA
Input or Open-Drain Output
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-11
Serial Host Interface
Table 2-10 Serial Host Interface Signals (continued)
Signal Name MOSI Signal Type Input or Output State During Reset Tri-Stated Signal Description SPI Master-Out-Slave-In--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for I2C slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when configured for the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant. SS Input Tri-Stated SPI Slave Select--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI master mode, this signal should be kept deasserted (pulled high). If it is asserted while configured as SPI master, a bus error condition is flagged. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. I2C Slave Address 2--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C master mode. This signal is tri-stated during hardware, software, and individual reset. Thus, there is no need for an external pull-up in this state. This input is 3.3V tolerant. HREQ Input or Output Tri-Stated Host Request--This signal is an active low Schmitt-trigger input when configured for the master mode but an active low output when configured for the slave mode. When configured for the slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the master mode, HREQ is an input. When asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. This signal is tri-stated during hardware, software, personal reset, or when the HREQ1-HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 3.3V tolerant.
HA0
Input
HA2
Input
DSP56367 Technical Data, Rev. 2.1 2-12 Freescale Semiconductor
Enhanced Serial Audio Interface
2.12
Signal Name HCKR
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals
Signal Type Input or Output State during Reset GPIO Disconnected Signal Description High Frequency Clock for Receiver--When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e.g., for external digital to analog converters [DACs]) or as an additional system clock. Port C 2--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PC2
Input, Output, or Disconnected
HCKT
Input or Output
GPIO Disconnected
High Frequency Clock for Transmitter--When programmed as an input, this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high frequency sample clock (e.g., for external DACs) or as an additional system clock. Port C 5--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PC5
Input, Output, or Disconnected
FSR
Input or Output
GPIO Disconnected
Frame Sync for Receiver--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PC1
Input, Output, or Disconnected
Port C 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-13
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Signal Name FST Signal Type Input or Output State during Reset GPIO Disconnected Signal Description Frame Sync for Transmitter--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port C 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SCKR Input or Output GPIO Disconnected Receiver Serial Clock--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PC0 Input, Output, or Disconnected Port C 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SCKT Input or output GPIO Disconnected Transmitter Serial Clock--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port C 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO5 SDI0 PC6 Output Input Input, Output, or Disconnected GPIO Disconnected Serial Data Output 5--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port C 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PC4
Input, Output, or Disconnected
PC3
Input, Output, or Disconnected
DSP56367 Technical Data, Rev. 2.1 2-14 Freescale Semiconductor
Enhanced Serial Audio Interface
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Signal Name SDO4 SDI1 PC7 Signal Type Output Input Input, Output, or Disconnected State during Reset GPIO Disconnected Signal Description Serial Data Output 4--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port C 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO3/ SDO3_1 SDI2/ SDI2_1 Output GPIO Disconnected Serial Data Output 3--When programmed as a transmitter, SDO3 is used to transmit data from the TX3 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 3. Input Serial Data Input 2--When programmed as a receiver, SDI2 is used to receive serial data into the RX2 serial receive shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 2. PC8/PE8 Input, Output, or Disconnected Port C 8--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 8 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO2/ SDO2_1 SDI3/ SDI3_1 Output GPIO Disconnected Serial Data Output 2--When programmed as a transmitter, SDO2 is used to transmit data from the TX2 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 2. Input Serial Data Input 3--When programmed as a receiver, SDI3 is used to receive serial data into the RX3 serial receive shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Input 3. PC9/PE9 Input, Output, or Disconnected Port C 9--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 9 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. SDO1/ SDO1_1 PC10/ PE10 Output GPIO Disconnected Serial Data Output 1--SDO1 is used to transmit data from the TX1 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 1. Input, Output, or disconnected Port C 10--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 10 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-15
Enhanced Serial Audio Interface_1
Table 2-11 Enhanced Serial Audio Interface Signals (continued)
Signal Name SDO0/ SDO0_1 PC11/ PE11 Signal Type Output State during Reset GPIO Disconnected Signal Description Serial Data Output 0--SDO0 is used to transmit data from the TX0 serial transmit shift register. When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0. Input, Output, or Disconnected Port C 11--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 11 signal. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
2.13
Signal Name FSR_1
Enhanced Serial Audio Interface_1
Table 2-12 Enhanced Serial Audio Interface_1 Signals
Signal Type Input or Output State during Reset GPIO Disconnected Signal Description Frame Sync for Receiver_1--This is the receiver frame sync input/output signal. In the asynchronous mode (SYN=0), the FSR pin operates as the frame sync input or output used by all the enabled receivers. In the synchronous mode (SYN=1), it operates as either the serial flag 1 pin (TEBE=0), or as the transmitter external buffer enable control (TEBE=1, RFSD=1). When this pin is configured as serial flag pin, its direction is determined by the RFSD bit in the RCCR register. When configured as the output flag OF1, this pin will reflect the value of the OF1 bit in the SAICR register, and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF1, the data value at the pin will be stored in the IF1 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode.
PE1
Input, Output, or Disconnected
Port E 1--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V.
FST_1
Input or Output
GPIO Disconnected
Frame Sync for Transmitter_1--This is the transmitter frame sync input/output signal. For synchronous mode, this signal is the frame sync for both transmitters and receivers. For asynchronous mode, FST is the frame sync for the transmitters only. The direction is determined by the transmitter frame sync direction (TFSD) bit in the ESAI transmit clock control register (TCCR). Port E 4--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V.
PE4
Input, Output, or Disconnected
DSP56367 Technical Data, Rev. 2.1 2-16 Freescale Semiconductor
Enhanced Serial Audio Interface_1
Table 2-12 Enhanced Serial Audio Interface_1 Signals (continued)
Signal Name SCKR_1 Signal Type Input or Output State during Reset GPIO Disconnected Signal Description Receiver Serial Clock_1--SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin in the synchronous mode (SYN=1). When this pin is configured as serial flag pin, its direction is determined by the RCKD bit in the RCCR register. When configured as the output flag OF0, this pin will reflect the value of the OF0 bit in the SAICR register, and the data in the OF0 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode. When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. PE0 Input, Output, or Disconnected Port E 0--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. SCKT_1 Input or Output GPIO Disconnected Transmitter Serial Clock_1--This signal provides the serial bit rate clock for the ESAI. SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode, or by all enabled transmitters in asynchronous mode. Port E 3--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. SDO5_1 SDI0_1 PE6 Output Input Input, Output, or Disconnected GPIO Disconnected Serial Data Output 5_1--When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0_1--When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. Port E 6--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. SDO4_1 SDI1_1 PE7 Output Input Input, Output, or Disconnected GPIO Disconnected Serial Data Output 4_1--When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1_1--When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. Port E 7--When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PE3
Input, Output, or Disconnected
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-17
SPDIF Transmitter Digital Audio Interface
2.14
Signal Name ACI
SPDIF Transmitter Digital Audio Interface
Table 2-13 Digital Audio Interface (DAX) Signals
Type Input State During Reset GPIO Disconnected Signal Description Audio Clock Input--This is the DAX clock input. When programmed to use an external clock, this input supplies the DAX clock. The external clock frequency must be 256, 384, or 512 times the audio sampling frequency (256 x Fs, 384 x Fs or 512 x Fs, respectively). Port D 0--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
PD0
Input, Output, or Disconnected
ADO PD1
Output Input, Output, or Disconnected
GPIO Disconnected
Digital Audio Data Output--This signal is an audio and non-audio output in the form of AES/EBU, CP340 and IEC958 data in a biphase mark format. Port D 1--When the DAX is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant.
2.15
Signal Name TIO0
Timer
Table 2-14 Timer Signal
Type Input or Output State during Reset Input Signal Description Timer 0 Schmitt-Trigger Input/Output--When timer 0 functions as an external event counter or in measurement mode, TIO0 is used as input. When timer 0 functions in watchdog, timer, or pulse modulation mode, TIO0 is used as output. The default mode after reset is GPIO input. This can be changed to output or configured as a timer input/output through the timer 0 control/status register (TCSR0). If TIO0 is not being used, it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input is 3.3 V tolerant.
DSP56367 Technical Data, Rev. 2.1 2-18 Freescale Semiconductor
JTAG/OnCE Interface
2.16
Signal Name TCK
JTAG/OnCE Interface
Table 2-15 JTAG/OnCE Interface
Signal Type Input State during Reset Input Signal Description Test Clock--TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 3.3V tolerant.
TDI
Input
Input
Test Data Input--TDI is a test data serial input signal used for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 3.3V tolerant.
TDO
Output
Tri-Stated
Test Data Output--TDO is a test data serial output signal used for test instructions and data. TDO is tri-statable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCK. Test Mode Select--TMS is an input signal used to sequence the test controller's state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input is 3.3V tolerant.
TMS
Input
Input
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 2-19
JTAG/OnCE Interface
NOTES
DSP56367 Technical Data, Rev. 2.1 2-20 Freescale Semiconductor
3
3.1
Specifications
Introduction
The DSP56367 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. NOTE This document contains information on a new product. Specifications and information herein are subject to change without notice. Finalized specifications may be published after further characterization and device qualifications are completed.
3.2
Maximum Ratings
CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are pulled to an appropriate logic voltage level (for example, either GND or VCC). The suggested value for a pull-up or pull-down resistor is 10 k. NOTE In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-1
Thermal Characteristics
Table 3-1 Maximum Ratings
Rating1 Supply Voltage Symbol VCCQL, VCCP VCCQH, VCCA, VCCD, VCCC, VCCH, VCCS, All "3.3V tolerant" input voltages Current drain per pin excluding VCC and GND Operating temperature range3 Storage temperature
1
Value1, 2
Unit V
-0.3 to + 2.0 -0.3 to + 4.0
GND - 0.3 to VCC + 0.7 10
V V mA
VIN I TJ TSTG
-40 to + 95 -55 to +125
C C
GND = 0 V, VCCP, VCCQL = 1.8 V 5%, TJ = -40xC to +95xC, CL = 50 pF All other VCC = 3.3 V 5%, TJ = -40xC to +95xC, CL = 50 pF 2 Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. 3 Temperatures below -0C are qualified for consumer applications.
3.3
Thermal Characteristics
Table 3-2 Thermal Characteristics
Characteristic Symbol RJA or JA RJC or JC JT TQFP Value 45.0 10.0 3.0 Unit
Natural Convection, Junction-to-ambient thermal resistance1,2 Junction-to-case thermal resistance3 Natural Convection, Thermal characterization parameter4
1
C/W C/W C/W
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 4 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
DSP56367 Technical Data, Rev. 2.1 3-2 Freescale Semiconductor
DC Electrical Characteristics
3.4
DC Electrical Characteristics
Table 3-3 DC Electrical Characteristics1
Characteristics Symbol VCC Min 1.71 Typ 1.8 Max 1.89 Unit V
Supply voltages * Core (VCCQL) * PLL(VCCP) Supply voltages * VCCQH * VCCA * VCCD * VCCC * VCCH * VCCS Input high voltage * D(0:23), BG, BB, TA, ESAI_1 (except SDO4_1) * MOD2/IRQ2, RESET, PINIT/NMI and all JTAG/ESAI_1/Timer/HDI08/DAX/(only SDO4_1)/SHI(SPI mode)
VCC
3.14
3.3
3.46
V
V VIH VIHP VIHP VIHX 2.0 2.0 1.5 0.8 x VCCQH -- -- -- -- VCCQH VCCQH + 03 max for both VIHP VCCQH + 03 max for both VIHP 0.8 x VCCQH V VIL VILP VILP VILX IIN ITSI VOH VOL -0.3 -0.3 -0.3 -0.3 -10 -10 2.4 -- -- -- -- -- -- -- -- -- 0.8 0.8 0.3 x VCC 0.2 x VCCQH 10 10 -- 0.4 A A V V mA ICCI ICCW ICCS -- -- -- -- CIN -- 58.0 7.3 2.0 1 -- 115 20 4 2.5 10 mA pF
* SHI(I2C mode) * EXTAL Input low voltage * D(0:23), BG, BB, TA, ESAI_1(except SDO4_1) * MOD2/IRQ2, RESET, PINIT/NMI and all JTAG/ESAI/Timer/HDI08/DAX/ESAI_1(only SDO4_1)/SHI(SPI mode) * SHI(I2C mode) * EXTAL Input leakage current High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage3 Output low voltage3 Internal supply current4 at internal clock of 150MHz * In Normal mode * In Wait mode * In Stop mode
5
PLL supply current Input capacitance6
1
VCCQL = 1.8 V 5%, TJ = -40C to +95C, CL = 50 pF All other VCC = 3.3 V 5%, TJ = -40C to +95C, CL = 50 pF 2 Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-3
AC Electrical Characteristics
3 4
This characteristic does not apply to PCAP. The Appendix A, "Power Consumption Benchmark" section provides a formula to compute the estimated current requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal supply current is measured with VCCQL = 1.8V, VCC(other) = 3.3V at TJ = 25C. Maximum internal supply current is measured with VCCQL = 1.89V, VCC(other) = 3.46V at TJ = 95C. 5 In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not allowed to float). 6 Periodically sampled and not 100% tested
3.5
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.4 V and a VIH minimum of 2.4 V for all pins except EXTAL. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal's transition. DSP56367 output levels are measured with the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively. NOTE Although the minimum value for the frequency of EXTAL is 0 MHz, the device AC test conditions are 15 MHz and rated speed.
3.6
Internal Clocks
Table 3-4 Internal Clocks
Expression1, 2 Characteristics Symbol Min Typ (Ef x MF)/(PDF x DF) Ef/2 Max -- -- f f TH -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF TL -- 0.49 x ETC x PDF x DF/MF 0.47 x ETC x PDF x DF/MF TC -- ETC -- -- ETC x PDF x DF/MF -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF -- ETC -- -- -- 0.51 x ETC x PDF x DF/MF 0.53 x ETC x PDF x DF/MF -- --
Internal operation frequency with PLL enabled Internal operation frequency with PLL disabled Internal clock high period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4
Internal clock low period * With PLL disabled * With PLL enabled and MF 4 * With PLL enabled and MF > 4
Internal clock cycle time with PLL enabled
DSP56367 Technical Data, Rev. 2.1 3-4 Freescale Semiconductor
External Clock Operation
Table 3-4 Internal Clocks (continued)
Expression1, 2 Characteristics Internal clock cycle time with PLL disabled Instruction cycle time
1
Symbol Min TC ICYC -- -- Typ 2 x ETC TC Max -- --
DF = Division Factor Ef = External frequency ETC = External clock cycle MF = Multiplication Factor PDF = Predivision Factor TC = internal clock cycle 2 Refer to the DSP56300 Family Manual for a detailed discussion of the PLL.
3.7
External Clock Operation
The DSP56367 system clock is an externally supplied square wave voltage source connected to EXTAL(Figure 3-1).
VIHC EXTAL VILC ETH 2 4 ETL Midpoint
3 ETC
Note: The midpoint is 0.5 (VIHC + VILC).
Figure 3-1 External Clock Timing Table 3-5 Clock Operation
No. 1 Characteristics Frequency of EXTAL (EXTAL Pin Frequency) The rise and fall time of this external clock should be 2 ns maximum. 2 EXTAL input high1, 2 * With PLL disabled (46.7%-53.3% duty cycle3)
3)
Symbol Ef
Min 2.0 ns
Max 150.0
ETH 3.11 ns 2.83 ns ETL
3
157.0 s
* With PLL enabled (42.5%-57.5% duty cycle 3 EXTAL input low1, 2
* With PLL disabled (46.7%-53.3% duty cycle ) * With PLL enabled (42.5%-57.5% duty cycle )
3
3.11 ns 2.83 ns
157.0 s
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-5
Phase Lock Loop (PLL) Characteristics
Table 3-5 Clock Operation (continued)
No. 4 EXTAL cycle time2 * With PLL disabled * With PLL enabled 7 Instruction cycle time = ICYC = TC4 * With PLL disabled * With PLL enabled
1 2
Characteristics
Symbol ETC
Min
Max
6.7 ns 6.7 ns ICYC 13.33 ns 6.67 ns
273.1 s
8.53 s
Measured at 50% of the input transition. The maximum value for PLL enabled is given for minimum VCO and maximum MF. 3 The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. 4 The maximum value for PLL enabled is given for minimum V CO and maximum DF.
3.8
Phase Lock Loop (PLL) Characteristics
Table 3-6 PLL Characteristics
Characteristics Min 30 Max 300 Unit MHz pF (MF x 580) - 100 MF x 830 (MF x 780) - 140 MF x 1470
VCO frequency when PLL enabled (MF x Ef x 2/PDF) PLL external capacitor (PCAP pin to VCCP) (CPCAP1) * @ MF 4 * @ MF > 4
1
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP can be computed from one of the following equations: (MF x 680)-120, for MF 4, or MF x 1100, for MF > 4.
DSP56367 Technical Data, Rev. 2.1 3-6 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
3.9
No. 8 9
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1
Characteristics Delay from RESET assertion to all pins at reset value2 Required RESET duration3 * Power on, external clock generator, PLL disabled * Power on, external clock generator, PLL enabled * Power on, Internal oscillator * During STOP, XTAL disabled * During STOP, XTAL enabled * During normal operation 50 x ETC 1000 x ETC 75000 x ETC 75000 x ETC 2.5 x TC 2.5 x TC 333.4 6.7 500 500 16.7 16.7 -- -- -- -- -- -- ns s s s ns ns ns 3.25 x TC + 2.0 20.25 x TC + 10 23.7 -- -- 145.0 ns TC -- 6.7 ns 3.25 x TC + 1.0 20.25 x TC + 5.0 22.7 -- 30.0 0.0 4.4 4.4 -- 140.0 -- -- -- -- ns ns ns ns ns 4.25 x TC + 2.0 7.25 x TC + 2.0 10 x TC + 5.0 30.3 50.3 71.7 -- -- -- ns Expression -- Min -- Max 26.0 Unit ns
10
Delay from asynchronous RESET deassertion to first external address output (internal reset deassertion)4 * Minimum * Maximum
11
Syn reset setup time from RESET * Maximum
12
Syn reset deassert delay time * Minimum * Maximum
13 14 15 16 17
Mode select setup time Mode select hold time Minimum edge-triggered interrupt request assertion width Minimum edge-triggered interrupt request deassertion width Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory access address out valid * Caused by first interrupt instruction fetch * Caused by first interrupt instruction execution
18
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to general-purpose transfer output valid caused by first interrupt instruction execution Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts5, 6, 7 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts5, 6, 7
19
(WS + 3.75) x TC - 10.94
--
Note 8
ns
20
(WS + 3.25) x TC - 10.94
--
Note 8
ns
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-7
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)
No. 21 Characteristics Delay from WR assertion to interrupt request deassertion for level sensitive fast interrupts5, 6, 7 * DRAM for all WS * SRAM WS = 1 * SRAM WS = 2, 3 * SRAM WS 4 22 Synchronous int setup time from IRQs NMI assertion to the CLKOUT trans. Synch. int delay time from the CLKOUT trans2 to the first external address out valid caused by first inst fetch * Minimum * Maximum 24 25 Duration for IRQA assertion to recover from Stop state Delay from IRQA assertion to fetch of first instruction (when exiting Stop)2, 8 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (Implies No Stop Delay) 26 Duration of level sensitive IRQA assertion to ensure interrupt service (when exiting Stop)2, 8 * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is enabled (OMR Bit 6 = 0) * PLL is not active during Stop (PCTL Bit 17 = 0) and Stop delay is not enabled (OMR Bit 6 = 1) * PLL is active during Stop (PCTL Bit 17 = 1) (implies no Stop delay) 27 Interrupt Requests Rate * HDI08, ESAI, ESAI_1, SHI, DAX, Timer * DMA * IRQ, NMI (edge trigger) * IRQ (level trigger) 12TC 8TC 8TC 12TC -- -- -- -- 80.0 53.0 53.0 80.0 PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (20.5 +/- 0.5) x TC 5.5 x TC -- -- 36.7 -- -- -- ms ms ns PLC x ETC x PDF + (128 K - PLC/2) x TC PLC x ETC x PDF + (23.75 +/- 0.5) x TC (8.25 0.5) x TC -- -- 51.7 -- -- 58.3 ms ms ns 9.25 x TC + 1.0 24.75 x TC + 5.0 0.6 x TC - 0.1 62.7 -- 3.9 -- 170.0 -- ns (WS + 3.5) x TC - 10.94 N/A 1.75 x TC - 4.0 2.75 x TC - 4.0 0.6 x TC - 0.1 -- -- -- -- 3.9 Note 8 Note 8 Note 8 Note 8 -- ns Expression Min Max Unit ns
23
ns
ns
DSP56367 Technical Data, Rev. 2.1 3-8 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
Table 3-7 Reset, Stop, Mode Select, and Interrupt Timing1 (continued)
No. 28 DMA Requests Rate * Data read from HDI08, ESAI, ESAI_1, SHI, DAX * Data write to HDI08, ESAI, ESAI_1, SHI, DAX * Timer * IRQ, NMI (edge trigger) 29
1 2 3
Characteristics
Expression
Min
Max
Unit ns
6TC 7TC 2TC 3TC 4.25 x TC + 2.0
-- -- -- 30.3
40.0 46.7 13.3 20.0 -- ns
Delay from IRQA, IRQB, IRQC, IRQD, NMI assertion to external memory (DMA source) access address out valid
4 5
6 7 8
VCCQH = 3.3 V 5%; VCC= 1.8V 5%; TJ = -40C to + 95C, CL = 50 pF Periodically sampled and not 100% tested. RESET duration is measured during the time in which RESET is asserted, VCC is valid, and the EXTAL input is active and valid. When the VCC is valid, but the other "required RESET duration" conditions (as specified above) have not been yet met, the device circuitry will not be in an initialized state that can result in significant power consumption and heat-up. Designs should minimize this state to the shortest possible duration. If PLL does not lose lock. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. WS = number of wait states (measured in clock cycles, number of TC). Use expression to compute maximum value. This timing depends on several settings: For PLL disable, using external clock (PCTL Bit 16 = 1), no stabilization delay is required and recovery time will be defined by the PCTL Bit 17 and OMR Bit 6 settings. For PLL enable, if PCTL Bit 17 is 0, the PLL is shutdown during Stop. Recovering from Stop requires the PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0 to 1000 cycles. This procedure occurs in parallel with the stop delay counter, and stop recovery will end when the last of these two events occurs: the stop delay counter completes count or PLL lock procedure completion. PLC value for PLL disable is 0. The maximum value for ETC is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 150 MHz it is 4096/150 MHz = 27.3 s). During the stabilization period, TC, TH, and TL will not be constant, and their width may vary, so timing may vary as well.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-9
Reset, Stop, Mode Select, and Interrupt Timing VIH RESET
9 8 All Pins Reset Value
10
A0-A17
First Fetch AA0460
Figure 3-2 Reset Timing
First Interrupt Instruction Execution/Fetch
A0-A17
RD 20 WR
21
IRQA, IRQB, IRQC, IRQD, NMI
17
19
a) First Interrupt Instruction Execution
General Purpose I/O
18 IRQA, IRQB, IRQC, IRQD, NMI b) General Purpose I/O
Figure 3-3 External Fast Interrupt Timing
DSP56367 Technical Data, Rev. 2.1 3-10 Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
IRQA, IRQB, IRQC, IRQD, NMI 15 IRQA, IRQB, IRQC, IRQD, NMI 16 AA0463
Figure 3-4 External Interrupt Timing (Negative Edge-Triggered)
RESET
VIH
13 14 MODA, MODB, MODC, MODD, PINIT VIH VIL VIH VIL IRQA, IRQB, IRQD, NMI
AA0465
Figure 3-5 Operating Mode Select Timing
24 IRQA
25 A0-A17 First Instruction Fetch AA0466
Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-11
External Memory Expansion Port (Port A)
26 IRQA
25 A0-A17 First IRQA Interrupt Instruction Fetch AA0467
Figure 3-7 Recovery from Stop State Using IRQA Interrupt Service
A0-A17
DMA Source Address
RD
WR 29 First Interrupt Instruction Execution AA1104
IRQA, IRQB, IRQC, IRQD, NMI
Figure 3-8 External Memory Access (DMA Source) Timing
3.10
3.10.1
External Memory Expansion Port (Port A)
SRAM Timing
Table 3-8 SRAM Read and Write Accesses
150 MHz Unit Min Max -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns 22.7 69.3 3.0 6.3 9.3 19.3 4.3 11.0
No. 100
Characteristics Address valid and AA assertion pulse width
Symbol
Expression1
tRC, tWC (WS + 2) x TC - 4.0 [2 WS 7] (WS + 3) x TC - 4.0 [WS 8] 0.75 x TC - 2.0[2 WS 3] 1.25 x TC - 2.0[WS 4] WS x TC - 4.0 [2 WS 3] (WS - 0.5) x TC - 4.0[WS 4] 1.25 x TC - 4.0[2 WS 7] 2.25 x TC - 4.0[WS 8]
101
Address and AA valid to WR assertion
tAS
102
WR assertion pulse width
tWP
103
WR deassertion to address not valid
tWR
DSP56367 Technical Data, Rev. 2.1 3-12 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-8 SRAM Read and Write Accesses (continued)
No. 104 105 106 107 108 109 Characteristics Address and AA valid to input data valid RD assertion to input data valid RD deassertion to data not valid (data hold time) Address valid to WR deassertion2 Data valid to WR deassertion (data setup time) Data hold time from WR deassertion Symbol tAA, tAC tOE tOHZ tAW (WS + 0.75) x TC - 4.0 [WS 2] Expression1 (WS + 0.75) x TC - 5.0 [WS 2] (WS + 0.25) x TC - 5.0 [WS 2] 150 MHz Unit Min -- -- 0.0 14.3 8.7 6.3 13.0 -2.0 -5.4 -- -- -- 4.3 11.0 17.7 7.7 14.3 9.3 12.7 19.3 1.3 11.0 6.3 13.0 3.7 0.0 Max 13.3 10.0 -- -- -- -- -- -- -- 1.9 8.5 15.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tDS (tDW) (WS - 0.25) x TC - 3.0 [WS 2] tDH 1.25 x TC - 2.0[2 WS 7] 2.25 x TC - 2.0 [WS 8] 0.25 x TC - 3.7 [2 WS 3] -0.25 x TC - 3.7 [WS 4] 0.25 x TC + 0.2 [2 WS 3] 1.25 x TC + 0.2 [4 WS 7] 2.25 x TC + 0.2 [WS 8] 1.25 x TC - 4.0 [2 WS 3] 2.25 x TC - 4.0 [4 WS 7] 3.25 x TC - 4.0 [WS 8] 1.75 x TC - 4.0 [2 WS 7] 2.75 x TC - 4.0 [WS 8] 2.0 x TC - 4.0 [2 WS 3] 2.5 x TC - 4.0 [4 WS 7] 3.5 x TC - 4.0 [WS 8] 0.5 x TC - 2.0 (WS + 0.25) x TC -4.0 1.25 x TC - 2.0 [2 WS 7] 2.25 x TC - 2.0 [WS 8] 0.25 x TC + 2.0
110
WR assertion to data active
--
111
WR deassertion to data high impedance
--
112
Previous RD deassertion to data active (write)
--
113
RD deassertion time
114
WR deassertion time
115 116 117
Address valid to RD assertion RD assertion pulse width RD deassertion to address not valid TA setup before RD or WR deassertion3 TA hold after RD or WR deassertion
118 119
1
WS is the number of wait states specified in the BCR. The value is given for the minimum for a given category. (For example, for a category of [2 WS 7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise. 2 Timings 100, 107 are guaranteed by design, not tested. 3 In the case of TA negation: timing 118 is relative to the deassertion edge of RD or WR were TA to remain active.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-13
External Memory Expansion Port (Port A)
100 A0-A17 AA0-AA2 113 RD 115 WR 104 119 TA D0-D23 Data In AA0468 118 105 106 116 117
Figure 3-9 SRAM Read Access
100 A0-A17 AA0-AA2 107 101 WR 114 RD 119 TA 108 109 Data Out 118 102 103
D0-D23
Figure 3-10 SRAM Write Access
DSP56367 Technical Data, Rev. 2.1 3-14 Freescale Semiconductor
External Memory Expansion Port (Port A)
3.10.2
DRAM Timing
The selection guides provided in Figure 3-11 and Figure 3-14 should be used for primary selection only. Final selection should be based on the timing provided in the following tables. As an example, the selection guide suggests that 4 wait states must be used for 100 MHz operation when using Page Mode DRAM. However, by using the information in the appropriate table, a designer may choose to evaluate whether fewer wait states might be used by determining which timing prevents operation at 100 MHz, running the chip at a slightly lower frequency (e.g., 95 MHz), using faster DRAM (if it becomes available), and control factors such as capacitive and resistive load to improve overall system performance.
DRAM Type (tRAC ns) Note: This figure should be use for primary selection. For exact and detailed timings see the following tables.
100
80
70
60
50 40 66 80 100 120
Chip Frequency (MHz)
1 Wait States 2 Wait States
3 Wait States 4 Wait States AA0472
Figure 3-11 DRAM Page Mode Wait States Selection Guide
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-15
External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, Three Wait States1, 2, 3
100 MHz No. Characteristics Symbol Expression4 Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 138 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1:0] = 00, 01-- not applicable * BRW[1:0] = 10 * BRW[1:0] = 11 139 140 141 142 143 144 145 146 147 148 149 150 151 152 CAS deassertion pulse width Column address valid to CAS assertion CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion tCP tASC tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH 4.75 x TC - 6.0 6.75 x TC - 6.0 1.5 x TC - 4.0 TC - 4.0 2.5 x TC - 4.0 4 x TC - 4.0 1.25 x TC - 4.0 0.75 x TC - 4.0 2.25 x TC - 4.2 3.5 x TC - 4.5 3.75 x TC - 4.3 3.25 x TC - 4.3 0.5 x TC - 4.0 2.5 x TC - 4.0 1.25 x TC - 4.3 3.5 x TC - 4.0 41.5 61.5 11.0 6.0 21.0 36.0 8.5 3.5 18.3 30.5 33.2 28.2 1.0 21.0 8.2 31.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCAC tAA tOFF tRSH tRHCP tCAS tCRP 2.5 x TC - 4.0 4.5 x TC - 4.0 2 x TC - 4.0 tPC 2 x TC 1.25 x TC 2 x TC - 7.0 3 x TC - 7.0 20.0 12.5 -- -- 0.0 21.0 41.0 16.0 Max -- -- 13.0 23.0 -- -- -- -- ns ns ns ns ns ns ns ns Unit
DSP56367 Technical Data, Rev. 2.1 3-16 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-9 DRAM Page Mode Timings, Three Wait States1, 2, 3 (continued)
100 MHz No. Characteristics Symbol Expression4 Min 153 154 155 156
1 2 3 4 5 6
Unit Max 18.0 -- -- 2.5 ns ns ns ns
RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance
tGA tGZ
2.5 x TC - 7.0
-- 0.0
0.75 x TC - 0.3 0.25 x TC
7.2 --
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals 4 x TC for read-after-read or write-after-write sequences). BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
Table 3-10 DRAM Page Mode Timings, Four Wait States1, 2, 3
100 MHz No. Characteristics Symbol Expression4 Min 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses 132 133 134 135 136 137 138 CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) Last CAS assertion to RAS deassertion Previous CAS deassertion to RAS deassertion CAS assertion pulse width Last CAS deassertion to RAS assertion5 * BRW[1-0] = 00, 01--Not applicable * BRW[1-0] = 10 * BRW[1-0] = 11 139 140 CAS deassertion pulse width Column address valid to CAS assertion tCP tASC tCAC tAA tOFF tRSH tRHCP tCAS tCRP -- 5.25 x TC - 6.0 7.25 x TC - 6.0 2 x TC - 4.0 TC - 4.0 -- 46.5 66.5 16.0 6.0 -- -- -- -- -- -- ns ns ns ns 3.5 x TC - 4.0 6 x TC - 4.0 2.5 x TC - 4.0 tPC Max ns 5 x TC 4.5 x TC 2.75 x TC - 5.7 3.75 x TC - 5.7 50.0 45.0 -- -- 0.0 31.0 56.0 21.0 -- -- 21.8 31.8 -- -- -- -- ns ns ns ns ns ns Unit
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-17
External Memory Expansion Port (Port A)
Table 3-10 DRAM Page Mode Timings, Four Wait States1, 2, 3 (continued)
100 MHz No. Characteristics Symbol Expression4 Min 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
1 2 3 4
Unit Max -- -- -- -- -- -- -- -- -- -- -- -- 26.8 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CAS assertion to column address not valid Last column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion CAS assertion to WR deassertion WR assertion pulse width Last WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) WR assertion to CAS assertion Last RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid6 WR assertion to data active WR deassertion to data high impedance
tCAH tRAL tRCS tRCH tWCH tWP tRWL tCWL tDS tDH tWCS tROH tGA tGZ
3.5 x TC - 4.0 5 x TC - 4.0 1.25 x TC - 4.0 1.25 x TC - 3.7 3.25 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 3.75 x TC - 4.3 0.5 x TC - 4.5 3.5 x TC - 4.0 1.25 x TC - 4.3 4.5 x TC - 4.0 3.25 x TC - 5.7
31.0 46.0 8.5 8.8 28.3 40.5 43.2 33.2 0.5 31.0 8.2 41.0 -- 0.0
0.75 x TC - 1.5 0.25 x TC
6.0 --
5 6
The number of wait states for Page mode access is specified in the DCR. The refresh period is specified in the DCR. The asynchronous delays specified in the expressions are valid for DSP56367. All the timings are calculated for the worst case. Some of the timings are better for specific cases (for example, tPC equals 3 x TC for read-after-read or write-after-write sequences). An expressions is used to calculate the maximum or minimum value listed, as appropriate. BRW[1-0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of-page access. RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
DSP56367 Technical Data, Rev. 2.1 3-18 Freescale Semiconductor
External Memory Expansion Port (Port A)
RAS 136 131 CAS 137 140 141 A0-A17 Row Add Column Address 151 145 Column Address 144 142 Last Column Address 143 147 139 138 135
WR 146 RD 155 150 149 D0-D23 Data Out Data Out Data Out AA0473 156 148
Figure 3-12 DRAM Page Mode Write Accesses
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-19
External Memory Expansion Port (Port A)
RAS 136 131 CAS 137 140 Row Add Column Address 143 WR 132 133 153 RD 134 154 D0-D23 Data In Data In Data In AA0474 152 139 141 Column Address 138 142 Last Column Address 135
A0-A17
Figure 3-13 DRAM Page Mode Read Accesses
DSP56367 Technical Data, Rev. 2.1 3-20 Freescale Semiconductor
External Memory Expansion Port (Port A) DRAM Type (tRAC ns)
Note: This figure should be use for primary selection. For exact and detailed timings see the following tables.
100
80
70
60
50 40 66 80 100 120
Chip Frequency (MHz)
4 Wait States 8 Wait States
11 Wait States 15 Wait States AA0475
Figure 3-14 DRAM Out-of-Page Wait States Selection Guide Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2
20 MHz3 No. Characteristics Symbol Expression Min 157 158 159 160 161 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion tRC tRAC tCAC tAA tOFF 1.75 x TC - 4.0 3.25 x TC - 4.0 1.75 x TC - 4.0 5 x TC 2.75 x TC - 7.5 1.25 x TC - 7.5 1.5 x TC - 7.5 250.0 -- -- -- 0.0 Max -- 130.0 55.0 67.5 -- Min 166.7 -- -- -- 0.0 Max -- 84.2 34.2 42.5 -- ns ns ns ns ns 30 MHz3 Unit
162 163 164
tRP tRAS tRSH
83.5 158.5 83.5
-- -- --
54.3 104.3 54.3
-- -- --
ns ns ns
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-21
External Memory Expansion Port (Port A)
Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued)
20 MHz3 No. Characteristics Symbol Expression Min 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR assertion RAS deassertion to WR assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC 2.75 x TC - 4.0 1.25 x TC - 4.0 1.5 x TC 2 1.25 x TC 2 2.25 x TC - 4.0 1.75 x TC - 4.0 1.75 x TC - 4.0 1.25 x TC - 4.0 0.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 2 x TC - 4.0 1.5 x TC - 3.8 0.75 x TC - 3.7 0.25 x TC - 3.7 1.5 x TC - 4.2 3 x TC - 4.2 4.5 x TC - 4.5 4.75 x TC - 4.3 4.25 x TC - 4.3 2.25 x TC - 4.0 1.75 x TC - 4.0 3.25 x TC - 4.0 3 x TC - 4.3 0.5 x TC - 4.0 1.25 x TC - 4.0 133.5 58.5 73.0 60.5 108.5 83.5 83.5 58.5 8.5 83.5 158.5 96.0 71.2 33.8 8.8 70.8 145.8 220.5 233.2 208.2 108.5 83.5 158.5 145.7 21.0 58.5 Max -- -- 77.0 64.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Min 87.7 37.7 48.0 39.7 71.0 54.3 54.3 37.7 4.3 54.3 104.3 62.7 46.2 21.3 4.6 45.8 95.8 145.5 154.0 137.4 71.0 54.3 104.3 95.7 12.7 37.7 Max -- -- 52.0 43.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 30 MHz3 Unit
DSP56367 Technical Data, Rev. 2.1 3-22 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-11 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued)
20 MHz3 No. Characteristics Symbol Expression Min 191 192 193 194 195
1 2
30 MHz3 Unit Min 146.0 -- 0.0 24.7 -- Max -- 125.8 -- -- 8.3 ns ns ns ns ns
Max -- 192.5 -- -- 12.5
RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid4 WR assertion to data active WR deassertion to data high impedance
tROH tGA tGZ
4.5 x TC - 4.0 4 x TC - 7.5
221.0 -- 0.0
0.75 x TC - 0.3 0.25 x TC
37.2 --
The number of wait states for out of page access is specified in the DCR. The refresh period is specified in the DCR. 3 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (Figure 3-14). 4 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ.
Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2, 3
100 MHz No. Characteristics Symbol Expression Min 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH 4.25 x TC - 4.0 7.75 x TC - 4.0 5.25 x TC - 4.0 6.25 x TC - 4.0 3.75 x TC - 4.0 2.5 x TC 4.0 1.75 x TC 4.0 5.75 x TC - 4.0 4.25 x TC - 4.0 4.25 x TC - 4.0 1.75 x TC - 4.0 12 x TC 6.25 x TC - 7.0 3.75 x TC - 7.0 4.5 x TC - 7.0 120.0 -- -- -- 0.0 38.5 73.5 48.5 58.5 33.5 21.0 13.5 53.5 38.5 38.5 13.5 Max -- 55.5 30.5 38.0 -- -- -- -- -- -- 29.0 21.5 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-23
External Memory Expansion Port (Port A)
Table 3-12 DRAM Out-of-Page and Refresh Timings, Eleven Wait States1, 2, 3 (continued)
100 MHz No. Characteristics Symbol Expression Min 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195
1 2
Unit Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 93.0 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid5 WR assertion to data active WR deassertion to data high impedance
tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ
0.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6 x TC - 4.0 3.0 x TC - 4.0 1.75 x TC - 4.0 0.25 x TC - 2.0 5 x TC - 4.2 7.5 x TC - 4.2 11.5 x TC - 4.5 11.75 x TC - 4.3 10.25 x TC - 4.3 5.75 x TC - 4.0 5.25 x TC - 4.0 7.75 x TC - 4.0 6.5 x TC - 4.3 1.5 x TC - 4.0 2.75 x TC - 4.0 11.5 x TC - 4.0 10 x TC - 7.0
3.5 48.5 73.5 56.0 26.0 13.5 0.5 45.8 70.8 110.5 113.2 103.2 53.5 48.5 73.5 60.7 11.0 23.5 111.0 -- 0.0
0.75 x TC - 0.3 0.25 x TC
7.2 --
The number of wait states for out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56367. 4 Either t RCH or tRRH must be satisfied for read cycles. 5 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ.
DSP56367 Technical Data, Rev. 2.1 3-24 Freescale Semiconductor
External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2
100 MHz No. Characteristics Symbol Expression3 Min 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 Random read or write cycle time RAS assertion to data valid (read) CAS assertion to data valid (read) Column address valid to data valid (read) CAS deassertion to data not valid (read hold time) RAS deassertion to RAS assertion RAS assertion pulse width CAS assertion to RAS deassertion RAS assertion to CAS deassertion CAS assertion pulse width RAS assertion to CAS assertion RAS assertion to column address valid CAS deassertion to RAS assertion CAS deassertion pulse width Row address valid to RAS assertion RAS assertion to row address not valid Column address valid to CAS assertion CAS assertion to column address not valid RAS assertion to column address not valid Column address valid to RAS deassertion WR deassertion to CAS assertion CAS deassertion to WR4 assertion RAS deassertion to WR4 assertion CAS assertion to WR deassertion RAS assertion to WR deassertion WR assertion pulse width tRC tRAC tCAC tAA tOFF tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tCP tASR tRAH tASC tCAH tAR tRAL tRCS tRCH tRRH tWCH tWCR tWP 16 x TC 8.25 x TC - 5.7 4.75 x TC - 5.7 5.5 x TC - 5.7 0.0 6.25 x TC - 4.0 9.75 x TC - 4.0 6.25 x TC - 4.0 8.25 x TC - 4.0 4.75 x TC - 4.0 3.5 x TC 2 2.75 x TC 2 7.75 x TC - 4.0 6.25 x TC - 6.0 6.25 x TC - 4.0 2.75 x TC - 4.0 0.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 7 x TC - 4.0 5 x TC - 3.8 1.75 x TC - 3.7 0.25 x TC - 2.0 6 x TC - 4.2 9.5 x TC - 4.2 15.5 x TC - 4.5 160.0 -- -- -- 0.0 58.5 93.5 58.5 78.5 43.5 33.0 25.5 73.5 56.5 58.5 23.5 3.5 58.5 93.5 66.0 46.2 13.8 0.5 55.8 90.8 150.5 Max -- 76.8 41.8 49.3 -- -- -- -- -- -- 37.0 29.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-25
External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States1, 2 (continued)
100 MHz No. Characteristics Symbol Expression3 Min 183 184 185 186 187 188 189 190 191 192 193 194 195
1 2
Unit Max -- -- -- -- -- -- -- -- -- 134.3 -- -- 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns
WR assertion to RAS deassertion WR assertion to CAS deassertion Data valid to CAS assertion (write) CAS assertion to data not valid (write) RAS assertion to data not valid (write) WR assertion to CAS assertion CAS assertion to RAS assertion (refresh) RAS deassertion to CAS assertion (refresh) RD assertion to RAS deassertion RD assertion to data valid RD deassertion to data not valid5 WR assertion to data active WR deassertion to data high impedance
tRWL tCWL tDS tDH tDHR tWCS tCSR tRPC tROH tGA tGZ
15.75 x TC - 4.3 14.25 x TC - 4.3 8.75 x TC - 4.0 6.25 x TC - 4.0 9.75 x TC - 4.0 9.5 x TC - 4.3 1.5 x TC - 4.0 4.75 x TC - 4.0 15.5 x TC - 4.0 14 x TC - 5.7
153.2 138.2 83.5 58.5 93.5 90.7 11.0 43.5 151.0 -- 0.0
0.75 x TC - 1.5 0.25 x TC
6.0 --
The number of wait states for an out-of-page access is specified in the DCR. The refresh period is specified in the DCR. 3 An expression is used to compute the maximum or minimum value listed (or both if the expression includes ). 4 Either t RCH or tRRH must be satisfied for read cycles. 5 RD deassertion always occurs after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ.
DSP56367 Technical Data, Rev. 2.1 3-26 Freescale Semiconductor
External Memory Expansion Port (Port A)
157 162 RAS 167 169 168 170 CAS 171 173 174 175 A0-A17 Row Address 172 177 191 WR 160 159 RD 158 192 Data In AA0476 193 168 179 Column Address 176 166 164 163 165 162
161
D0-D23
Figure 3-15 DRAM Out-of-Page Read Access
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-27
External Memory Expansion Port (Port A)
157 162 163 165 162
RAS 167 169 168 170 CAS 171 173 172
164
166
174 176
A0-A17
Row Address 181
Column Address
175 188 WR 182 180
184 183 RD
187 186 185 194 195
D0-D23
Data Out AA0477
Figure 3-16 DRAM Out-of-Page Write Access
DSP56367 Technical Data, Rev. 2.1 3-28 Freescale Semiconductor
External Memory Expansion Port (Port A)
157 162 RAS 190 170 CAS 165 163 162
189 177 WR AA0478
Figure 3-17 DRAM Refresh Access
3.10.3
Arbitration Timings
Table 3-14 Asynchronous Bus Arbitration Timing1, 2, 3
150 MHz
No.
Characteristics
Expression Min Max 21.7 --
Unit
250 251
1 2
BB assertion window from BG input negation. Delay from BB assertion to BG assertion
2 .5* Tc + 5 2 * Tc + 5
-- 18.3
ns ns
Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode. If Asynchronous Arbitration mode is active, none of the timings in Table 3-14 is required. 3 In order to guarantee timings 250, and 251, it is recommended to assert BG inputs to different 56300 devices (on the same bus) in a non overlap manner as shown in Figure 3-18.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-29
External Memory Expansion Port (Port A)
BG1
BB 250
BG2 251
Figure 3-18 Asynchronous Bus Arbitration Timing
BG1
BG2
250+251
Figure 3-19 Asynchronous Bus Arbitration Timing
3.10.4
Background explanation for Asynchronous Bus Arbitration:
The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs. These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is negated. This is the reason for timing 250. Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided.
DSP56367 Technical Data, Rev. 2.1 3-30 Freescale Semiconductor
Parallel Host Interface (HDI08) Timing
3.11
Parallel Host Interface (HDI08) Timing
Table 3-15 Host Interface (HDI08) Timing1, 2, 3
150 MHz
No. 317
Characteristics Read data strobe assertion width4 HACK read assertion width
Expression Min TC + 9.9 16.7 Max --
Unit ns
318
Read data strobe deassertion width4 HACK read deassertion width Read data strobe deassertion width4 after "Last Data Register" reads5, 6, or between two consecutive CVR, ICR, or ISR reads7 HACK deassertion width after "Last Data Register" reads5, 6
--
9.9
--
ns
319
2.5 x TC + 6.6
23.3
--
ns
320
Write data strobe assertion width8 HACK write assertion width
--
13.2
--
ns
321
Write data strobe deassertion width8 HACK write deassertion width * after ICR, CVR and "Last Data Register" writes5 * after IVR writes, or * after TXH:TXM writes (with HBE=0), or * after TXL:TXM writes (with HBE=1) 2.5 x TC + 6.6 23.3 16.5 -- --
ns
322 323 324
HAS assertion width HAS deassertion to data strobe assertion9 Host data input setup time before write data strobe deassertion8 Host data input setup time before HACK write deassertion
-- -- --
9.9 0.0 9.9
-- -- --
ns ns ns
325
Host data input hold time after write data strobe deassertion8 Host data input hold time after HACK write deassertion
--
3.3
--
ns
326
Read data strobe assertion to output data active from high impedance4 HACK read assertion to output data active from high impedance
--
3.3
--
ns
327
Read data strobe assertion to output data valid4 HACK read assertion to output data valid
--
--
24.2
ns
328
Read data strobe deassertion to output data high impedance4 HACK read deassertion to output data high impedance
--
--
9.9
ns
329
Output data hold time after read data strobe deassertion4 Output data hold time after HACK read deassertion
--
3.3
--
ns
330 331
HCS assertion to read data strobe deassertion4 HCS assertion to write data strobe deassertion8
TC +9.9 --
16.7 9.9
-- --
ns ns
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-31
Parallel Host Interface (HDI08) Timing
Table 3-15 Host Interface (HDI08) Timing1, 2, 3 (continued)
150 MHz No. 332 333 334 335 336 Characteristics HCS assertion to output data valid HCS hold time after data strobe deassertion9 Address (AD7-AD0) setup time before HAS deassertion (HMUX=1) Address (AD7-AD0) hold time after HAS deassertion (HMUX=1) A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W setup time before data strobe assertion9 * Read * Write 337 A10-A8 (HMUX=1), A2-A0 (HMUX=0), HR/W hold time after data strobe deassertion9 Delay from read data strobe deassertion to host request assertion for "Last Data Register" read4, 5, 10 Delay from write data strobe deassertion to host request assertion for "Last Data Register" write5, 8, 10 Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 0)5, 9, 10 Delay from data strobe assertion to host request deassertion for "Last Data Register" read or write (HROD = 1, open drain Host Request)5, 9, 10, 11 Delay from DMA HACK deassertion to HOREQ assertion * For "Last Data Register" read5 * For "Last Data Register" write5 * For other cases 343 Delay from DMA HACK assertion to HOREQ deassertion * HROD = 0 344
5
Expression Min -- -- -- -- -- 0.0 4.7 3.3 Max 19.1 -- -- --
Unit ns ns ns ns ns
--
0 4.7
-- -- -- ns
--
3.3
338
TC 2 x TC --
6.7
--
ns
339
13.4
--
ns
340
--
19.1
ns
341
--
--
300.0
ns
342
ns 2 x TC + 19.1 1.5 x TC + 19.1 32.5 29.2 0.0 -- -- -- -- -- 20.2 ns
Delay from DMA HACK assertion to HOREQ deassertion for "Last Data Register" read or write * HROD = 1, open drain Host Request5, 11
--
--
300.0
ns
1 2 3 4 5 6 7 8
See Host Port Usage Considerations in the DSP56367 User's Manual. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF The read data strobe is HRD in the dual data strobe mode and HDS in the single data strobe mode. The "last data register" is the register at address $7, which is the last location to be read or written in data transfers. This timing is applicable only if a read from the "last data register" is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HOREQ signal. This timing is applicable only if two consecutive reads from one of these registers are executed. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
DSP56367 Technical Data, Rev. 2.1 3-32 Freescale Semiconductor
Parallel Host Interface (HDI08) Timing
9
The data strobe is host read (HRD) or host write (HWR) in the dual data strobe mode and host data strobe (HDS) in the single data strobe mode. 10 The host request is HOREQ in the single host request mode and HRRQ and HTRQ in the double host request mode. 11 In this calculation, the host request signal is pulled up by a 4.7 k resistor in the open-drain mode.
317 HACK 327 326 HD7-HD0 329 328
318
HOREQ AA1105
Figure 3-20 Host Interrupt Vector Register (IVR) Read Timing Diagram
HA0-HA2 336 330 HCS 337 333
317 HRD, HDS 318 328 332 327 326 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ 338 319 329
AA0484
Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-33
Parallel Host Interface (HDI08) Timing
HA0-HA2 336 331 333 HCS 337
320 HWR, HDS 321 324 325 HD0-HD7 340 341 HOREQ, HRRQ, HTRQ AA0485 339
Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus
DSP56367 Technical Data, Rev. 2.1 3-34 Freescale Semiconductor
Parallel Host Interface (HDI08) Timing
HA8-HA10 336 322 HAS 323 337
317 HRD, HDS 334 335 327 328 329 HAD0-HAD7 Address 326 340 341 HOREQ, HRRQ, HTRQ AA0486 338 Data 318 319
Figure 3-23 Read Timing Diagram, Multiplexed Bus
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-35
Parallel Host Interface (HDI08) Timing
HA8-HA10 336
322 HAS
323
320 HWR, HDS 334 335 HAD0-HAD7 Address Data 340 341 HOREQ, HRRQ, HTRQ AA0487 339 324 321 325
Figure 3-24 Write Timing Diagram, Multiplexed Bus
HOREQ (Output)
343 344 320 342
321
HACK (Input)
TXH/M/L Write 324 325
H0-H7 (Input)
Data Valid
Figure 3-25 Host DMA Write Timing Diagram
DSP56367 Technical Data, Rev. 2.1 3-36 Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
HOREQ (Output)
343 342 317 318 342
HACK (Input)
327 326
RXH Read 328 329 Data Valid
H0-H7 (Output)
Figure 3-26 Host DMA Read Timing Diagram
3.12
No. 140
Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing
Characteristics1 Tolerable spike width on clock or data in Mode -- Filter Mode Bypassed Narrow Wide Expression2 -- -- -- 6 x TC+46 6 x TC+152 6 x TC+223 0.5 x tSPICC -10 0.5 x tSPICC -10 0.5 x tSPICC -10 2.5 x TC + 12 2.5 x TC + 102 2.5 x TC + 189 0.5 x tSPICC -10 0.5 x tSPICC -10 0.5 x tSPICC -10 2.5 x TC + 12 2.5 x TC + 102 2.5 x TC + 189 28.8 118.8 205.8 -- -- -- ns Min -- -- -- 86.2 192.2 263.2 38 91 126.5 28.8 118.8 205.8 38 Max 0 50 100 -- -- -- -- -- -- -- -- -- -- ns ns ns ns Unit ns
141
Minimum serial clock cycle = tSPICC(min)
Master
Bypassed Narrow Wide
142
Serial clock high period
Master
Bypassed Narrow Wide
Slave
Bypassed Narrow Wide
143
Serial clock low period
Master
Bypassed Narrow Wide
Slave
Bypassed Narrow Wide
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-37
Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing (continued)
No. 144 Characteristics1 Serial clock rise/fall time Mode Master Slave 146 SS assertion to first SCK edge CPHA = 0 Slave Filter Mode -- -- Bypassed Narrow Wide CPHA = 1 Slave Bypassed Narrow Wide 147 Last SCK edge to SS not asserted Slave Bypassed Narrow Wide 148 Data input valid to SCK edge (data input set-up time) Master/ Slave Bypassed Narrow Wide 149 SCK last sampling edge to data input not valid Master/ Slave Bypassed Narrow Wide 150 151 152 SS assertion to data out active SS deassertion to data high impedance3 Slave Slave -- -- Bypassed Narrow Wide 153 SCK edge to data out not valid (data out hold time) Master/ Slave Bypassed Narrow Wide 154 157 SS assertion to data out valid (CPHA = 0) First SCK sampling edge to HREQ output deassertion Slave Slave -- Bypassed Narrow Wide 158 Last SCK sampling edge to HREQ output not deasserted (CPHA = 1) Slave Bypassed Narrow Wide 159 SS deassertion to HREQ output not deasserted (CPHA = 0) Slave -- Expression2 -- -- 3.5 x TC + 15 0 0 10 0 0 12 102 189 0 MAX{(20-TC), 0} MAX{(40-TC), 0} 2.5 x TC + 10 2.5 x TC + 30 2.5 x TC + 50 2 9 2 x TC + 33 2 x TC + 123 2 x TC + 210 TC + 5 TC + 55 TC + 106 TC + 33 2.5 x TC + 30 2.5 x TC + 120 2.5 x TC + 217 2.5 x TC + 30 2.5 x TC + 80 2.5 x TC + 136 2.5 x TC + 30 Min -- -- 38.5 0 0 10 0 0 12 102 189 0 13.3 33.3 26.8 46.8 66.8 2 -- -- -- -- 11.7 61.7 112.7 -- -- -- -- 46.8 96.8 152.8 46.8 Max 10 2000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 46.4 136.4 223.4 -- -- -- 39.7 46.8 136.8 233.8 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
SCK edge to data out valid (data out delay Master/ time) Slave
DSP56367 Technical Data, Rev. 2.1 3-38 Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
Table 3-16 Serial Host Interface SPI Protocol Timing (continued)
No. 160 161 Characteristics1 SS deassertion pulse width (CPHA = 0) HREQ in assertion to first SCK edge Mode Slave Master Filter Mode -- Bypassed Narrow Wide 162 HREQ in deassertion to last SCK sampling edge (HREQ in set-up time) (CPHA = 1) First SCK edge to HREQ in not asserted (HREQ in hold time)
1 2
Expression2 TC + 6 0.5 x tSPICC + 2.5 x TC + 43
Min 12.7 97.8
Max -- -- -- -- --
Unit ns ns
0.5 x tSPICC + 2.5 x TC + 43 160.8 0.5 x tSPICC + 2.5 x TC + 43 196.8 0 0
Master
--
ns
163
Master
--
0
0
--
ns
VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit SHI testing to lower clock frequencies. 3 Periodically sampled, not 100% tested
SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) AA0271 MSB 148 LSB Valid 153 LSB 149 141 144 144 144 141 144
Figure 3-27 SPI Master Timing (CPHA = 0)
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-39
Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid 152 MOSI (Output) 161 163 HREQ (Input) AA0272 MSB 162 LSB Valid 153 LSB 148 149 144 141 144 144 141 144
Figure 3-28 SPI Master Timing (CPHA = 1)
DSP56367 Technical Data, Rev. 2.1 3-40 Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input) HREQ (Output)
AA0273 MSB Valid LSB Valid
141 144 144 160
147
142 143
141 144 144
152 153 MSB
153
151 LSB 148 149
157
159
Figure 3-29 SPI Slave Timing (CPHA = 0)
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-41
Serial Host Interface (SHI) I2C Protocol Timing
SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 142 143 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 149 MOSI (Input) MSB Valid 157 HREQ (Output) AA0274 LSB Valid 158 MSB 148 149 152 153 151 LSB 144 144 144 141 144 147
Figure 3-30 SPI Slave Timing (CPHA = 1)
3.13
Serial Host Interface (SHI) I2C Protocol Timing
Table 3-17 SHI I2C Protocol Timing
Standard I2C
No.
Characteristics1, 2, 3 Tolerable spike width on SCL or SDA * Filters bypassed * Narrow filters enabled * Wide filters enabled
Symbol/ Expression --
Standard4, 5 Min Max
Fast-Mode5, 6 Min Max
Unit
ns -- -- -- 0 50 100 100 -- -- -- -- -- -- -- -- 2.5 1.3 0.6 0.6 0 50 100 400 -- -- -- -- kHz s s s s
171 SCL clock frequency 171 SCL clock cycle 172 Bus free time 173 Start condition set-up time 174 Start condition hold time
FSCL TSCL TBUF TSU;STA THD;STA
-- 10 4.7 4.7 4.0
DSP56367 Technical Data, Rev. 2.1 3-42 Freescale Semiconductor
Serial Host Interface (SHI) I2C Protocol Timing
Table 3-17 SHI I2C Protocol Timing (continued)
Standard I2C No. 175 SCL low period 176 SCL high period 177 SCL and SDA rise time 178 SCL and SDA fall time 179 Data set-up time 180 Data hold time 181 DSP clock frequency * Filters bypassed * Narrow filters enabled * Wide filters enabled 182 SCL low to data out valid 183 Stop condition setup time 184 HREQ in deassertion to last SCL edge (HREQ in set-up time) 186 First SCL sampling edge to HREQ output deassertion2 * Filters bypassed * Narrow filters enabled * Wide filters enabled 187 Last SCL edge to HREQ output not deasserted2 * Filters bypassed * Narrow filters enabled * Wide filters enabled 188 HREQ in assertion to first SCL edge * Filters bypassed * Narrow filters enabled * Wide filters enabled 187 First SCL edge to HREQ in not asserted (HREQ in hold time.)
1 2 3 4 5 6
Characteristics1, 2, 3
Symbol/ Expression TLOW THIGH TR TF TSU;DAT THD;DAT FDSP
Standard4, 5 Min 4.7 4.0 -- -- 250 0.0 Max -- -- 1000 300 -- --
Fast-Mode5, 6 Min 1.3 1.3 20 + 0.1 x Cb 20 + 0.1 x Cb 100 0.0 Max -- -- 300 300 -- 0.9
Unit
s s ns ns ns s MHz
10.6 11.8 13.1 TVD;DAT TSU;STO tSU;RQI TNG;RQO 2 x TC + 30 2 x TC + 120 2 x TC + 208 TAS;RQO 2 x TC + 30 2 x TC + 80 2 x TC + 135 TAS;RQI 0.5 x TI2CCP 0.5 x TC - 21 4327 4282 4238 tHO;RQI 0.0 50 100 155 -- -- -- -- 4.0 0.0
-- -- -- 3.4 -- --
28.5 39.7 61.0 -- 0.6 0.0
-- -- -- 0.9 -- -- s s ns
ns 50 140 228 -- -- -- 50 140 228 ns -- -- -- 50 100 155 -- -- -- ns -- -- -- -- 927 882 838 0.0 -- -- -- -- ns
VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF Pull-up resistor: RP (min) = 1.5 kOhm Capacitive load: Cb (max) = 400 pF It is recommended to enable the wide filters when operating in the I2C Standard Mode. The timing values are derived from frequencies not exceeding 100 MHz. It is recommended to enable the narrow filters when operating in the I2C Fast Mode.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-43
Serial Host Interface (SHI) I2C Protocol Timing
3.13.1
Programming the Serial Clock
2
The programmed serial clock cycle, T I CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control register). The expression for T I CCP is
2
T where
I CCP
2
= [ T C x 2 x ( H DM [ 7 :0 ] + 1 ) x ( 7 x ( 1 - HRS ) + 1 ) ]
HRS is the prescaler rate select bit. When HRS is cleared, the fixed divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected. In I2C mode, the user may select a value for the programmed serial clock cycle from 6 x TC ( if HDM [ 7 :0 ] = $02 and HRS = 1 ) to 4096 x T C ( if HDM [ 7 :0 ] = $FF and HRS = 0 ) The programmed serial clock cycle (TI CCP ), SCL rise time (TR), and the filters selected should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as shown in Table 3-18.
2
Table 3-18 SCL Serial Clock Cycle (TSCL) Generated as Master
Filters bypassed Narrow filters enabled Wide filters enabled
TI2CCP + 2.5 x TC + 45ns + TR TI2CCP + 2.5 x TC + 135ns + TR TI2CCP + 2.5 x TC + 223ns + TR
EXAMPLE:
For DSP clock frequency of 100 MHz (i.e. TC = 10ns), operating in a standard mode I2C environment (FSCL = 100 kHz (i.e. TSCL = 10s), TR = 1000ns), with wide filters enabled: T
I CCP
2
= 10s - 2.5 x 10ns - 223ns - 1000ns = 8752ns
Choosing HRS = 0 gives HDM [ 7 :0 ] = ( 8752ns ) ( 2 x 10ns x 8 ) - 1 = 53.7 Thus the HDM[7:0] value should be programmed to $36 (=54). The resulting TI CCP will be:
2
T
I CCP
2
= [ T C x 2 x ( H DM [ 7 :0 ] + 1 ) x ( 7 x ( 1 - 0 ) + 1 ) ] = [ 10ns x 2 x ( 54 + 1 ) x ( 7 x ( 1 - 0 ) + 1 ) ]
2
T
I CCP
2
T
I CCP
= [ 10 ns x 2 x 54 x 8 ] = 8640ns
DSP56367 Technical Data, Rev. 2.1 3-44 Freescale Semiconductor
Enhanced Serial Audio Interface Timing
171 173 SCL 177 172 179 SDA Stop Start 174 189 188 HREQ AA0275 MSB 186 184 187 LSB 182 ACK 183 Stop 178 180 176 175
Figure 3-31 I2C Timing
3.14
No. 430
Enhanced Serial Audio Interface Timing
Table 3-19 Enhanced Serial Audio Interface Timing1, 2
Characteristics3, 4, 5 Clock cycle7 Symbol tSSICC Expression 4 x TC 3 x TC TXC:max[3*tc; t454] Min 26.8 20.1 26.5 Max -- -- -- Condition6 i ck x ck x ck Unit ns
431
Clock high period * For internal clock * For external clock
-- 2 x TC - 10.0 1.5 x TC -- 2 x TC - 10.0 1.5 x TC -- -- 3.4 10.0 -- -- -- -- 37.0 22.0 37.0 22.0 39.0 24.0 39.0 24.0 x ck i ck a x ck i ck a x ck i ck a x ck i ck a 3.4 10.0 -- --
ns
432
Clock low period * For internal clock * For external clock
ns
433
RXC rising edge to FSR out (bl) high
ns
434
RXC rising edge to FSR out (bl) low
--
--
-- --
ns
435
RXC rising edge to FSR out (wr) high8
--
--
-- --
ns
436
RXC rising edge to FSR out (wr) low8
--
--
-- --
ns
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-45
Enhanced Serial Audio Interface Timing
Table 3-19 Enhanced Serial Audio Interface Timing1, 2 (continued)
No. 437 Characteristics3, 4, 5 RXC rising edge to FSR out (wl) high Symbol -- Expression -- Min -- -- 438 RXC rising edge to FSR out (wl) low -- -- -- -- 439 Data in setup time before RXC (SCK in synchronous mode) falling edge Data in hold time after RXC falling edge -- -- 0.0 19.0 -- -- 5.0 3.0 441 FSR input (bl, wr) high before RXC falling edge8 -- -- 23.0 1.0 442 FSR input (wl) high before RXC falling edge -- -- 23.0 1.0 443 FSR input hold time after RXC falling edge -- -- 3.0 0.0 444 Flags input setup before RXC falling edge -- -- 0.0 19.0 445 Flags input hold time after RXC falling edge -- -- 6.0 0.0 446 TXC rising edge to FST out (bl) high -- -- -- -- 447 TXC rising edge to FST out (bl) low -- -- -- -- 448 TXC rising edge to FST out (wr) high8 -- -- -- -- 449 TXC rising edge to FST out (wr) low8 -- -- -- -- 450 TXC rising edge to FST out (wl) high -- -- -- -- 451 TXC rising edge to FST out (wl) low -- -- -- -- 452 TXC rising edge to data out enable from high impedance TXC rising edge to transmitter #0 drive enable assertion -- -- -- -- -- -- -- -- Max 36.0 21.0 37.0 22.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29.0 15.0 31.0 17.0 31.0 17.0 33.0 19.0 30.0 16.0 31.0 17.0 31.0 17.0 34.0 20.0 Condition6 x ck i ck a x ck i ck a x ck i ck x ck i ck x ck i ck a x ck i ck a x ck i ck a x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit ns
440
453
DSP56367 Technical Data, Rev. 2.1 3-46 Freescale Semiconductor
Enhanced Serial Audio Interface Timing
Table 3-19 Enhanced Serial Audio Interface Timing1, 2 (continued)
No. 454 Characteristics3, 4, 5 TXC rising edge to data out valid Symbol -- Expression 23 + 0.5 x TC 21.0 455 TXC rising edge to data out high impedance9 -- -- Min -- -- -- -- 456 TXC rising edge to transmitter #0 drive enable deassertion9 FST input (bl, wr) setup time before TXC falling edge8 FST input (wl) to data out enable from high impedance FST input (wl) to transmitter #0 drive enable assertion FST input (wl) setup time before TXC falling edge -- -- -- -- -- -- 2.0 21.0 -- -- -- Max 26.5 21.0 31.0 16.0 34.0 20.0 -- -- 27.0 Condition6 x ck i ck x ck i ck x ck i ck x ck i ck -- ns ns ns ns Unit ns
457
458
459
--
--
--
31.0
--
ns
460
--
--
2.0 21.0
-- -- -- -- 32.0 18.0 -- 27.5 27.5
x ck i ck x ck i ck x ck i ck
ns
461
FST input hold time after TXC falling edge
--
--
4.0 0.0
ns
462
Flag output valid after TXC rising edge
--
--
-- --
ns
463 464 465
1 2 3 4
HCKR/HCKT clock cycle HCKT input rising edge to TXC output HCKR input rising edge to RXC output
-- -- --
-- -- --
40.0 -- --
ns ns ns
5
6
7
The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit ESAI testing to lower clock frequencies. ESAI_1 specs match those of ESAI_0. VCC = 1.8 V 5%; TJ = -40C to +95C, CL = 50 pF i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that TXC and RXC are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length wr = word length relative TXC(SCKT pin) = transmit clock RXC(SCKR pin) = receive clock FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-47
Enhanced Serial Audio Interface Timing
8
The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit clock of the first word in frame. 9 Periodically sampled and not 100% tested.
430 431 TXC (Input/Output) 446 FST (Bit) Out 450 FST (Word) Out 451 447 432
454 452
454 455 First Bit Last Bit
Data Out 459
Transmitter #0 Drive Enable
457 461
453
456
FST (Bit) In 458 460 461
FST (Word) In 462 Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. AA0490 See Note
Figure 3-32 ESAI Transmitter Timing
DSP56367 Technical Data, Rev. 2.1 3-48 Freescale Semiconductor
Enhanced Serial Audio Interface Timing
430 431 RXC (Input/Output) 433 FSR (Bit) Out 437 FSR (Word) Out 440 439 Data In 441 FSR (Bit) In 442 FSR (Word) In 444 Flags In AA0491 445 443 443 First Bit Last Bit 438 432
434
Figure 3-33 ESAI Receiver Timing
HCKT
SCKT (output)
463
464
Figure 3-34 ESAI HCKT Timing
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-49
Digital Audio Transmitter Timing
HCKR
SCKR (output)
463
465
Figure 3-35 ESAI HCKR Timing
3.15
Digital Audio Transmitter Timing
Table 3-20 Digital Audio Transmitter Timing
150 MHz No. Characteristic ACI frequency1 220 221 222 223 ACI period ACI high duration ACI low duration ACI rising edge to ADO valid Expression Min 1 / (2 x TC) 2 x TC 0.5 x TC 0.5 x TC 1.5 x TC -- 13.4 3.4 3.4 -- Max 75 -- -- -- 10.0 MHz ns ns ns ns Unit
1
In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56367 internal clock frequency. For example, if the DSP56367 is running at 150 MHz internally, the ACI frequency should be less than 75 MHz.
ACI 220 223 ADO AA1280 221 222
Figure 3-36 Digital Audio Transmitter Timing
DSP56367 Technical Data, Rev. 2.1 3-50 Freescale Semiconductor
Timer Timing
3.16
Timer Timing
Table 3-21 Timer Timing1
150 MHz No. Characteristics Expression Min 480 481 TIO Low TIO High 2 x TC + 2.0 2 x TC + 2.0 15.4 15.4 Max -- -- ns ns Unit
1
VCC = 1.8 V 0.09 V; TJ = -40C to +95C, CL = 50 pF
TIO 480 481 AA0492
Figure 3-37 TIO Timer Event Input Restrictions
3.17
No. 4902 491 492 493 4942 495 496
1 2
GPIO Timing
Table 3-22 GPIO Timing
Characteristics1 EXTAL edge to GPIO out valid (GPIO out delay time) EXTAL edge to GPIO out not valid (GPIO out hold time) GPIO In valid to EXTAL edge (GPIO in set-up time) EXTAL edge to GPIO in not valid (GPIO in hold time) Fetch to EXTAL edge before GPIO change GPIO out rise time GPIO out fall time 6.75 x TC-1.8 -- -- Expression Min -- 4.8 10.2 1.8 43.4 -- -- Max 32.8 -- -- -- -- 13 13 Unit ns ns ns ns ns ns ns
VCC = 1.8 V 0.09 V; TJ = -40C to +95C, CL = 50 pF Valid only when PLL enabled with multiplication factor equal to one.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-51
JTAG Timing
EXTAL (Input) 490 491 GPIO (Output) 492 GPIO (Input) Valid 493
A0-A17 494 Fetch the instruction MOVE X0,X:(R0); X0 contains the new value of GPIO and R0 contains the address of GPIO data register. GPIO (Output) 495 496
Figure 3-38 GPIO Timing
3.18
JTAG Timing
Table 3-23 JTAG Timing1, 2
All frequencies
No.
Characteristics Min Max 22.0 -- -- 3.0 -- -- 40.0 40.0 --
Unit
500 501 502 503 504 505 506 507 508
TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time in Crystal mode TCK clock pulse width measured at 1.5 V TCK rise and fall times Boundary scan input data setup time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data setup time
0.0 45.0 20.0 0.0 5.0 24.0 0.0 0.0 5.0
MHz ns ns ns ns ns ns ns ns
DSP56367 Technical Data, Rev. 2.1 3-52 Freescale Semiconductor
JTAG Timing
Table 3-23 JTAG Timing1, 2 (continued)
All frequencies No. Characteristics Min 509 510 511
1 2
Unit Max -- 44.0 44.0 ns ns ns
TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance
25.0 0.0 0.0
VCC = 1.8 V 0.09 V; TJ = -40C to +95C, CL = 50 pF All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
501 502 TCK (Input) VIH 503 VM VIL 503 AA0496 502 VM
Figure 3-39 Test Clock Input Timing Diagram
TCK (Input)
VIL 504
VIH 505
Data Inputs 506 Data Outputs 507 Data Outputs 506 Data Outputs
Input Data Valid
Output Data Valid
Output Data Valid AA0497
Figure 3-40 Boundary Scan (JTAG) Timing Diagram
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-53
JTAG Timing
TCK (Input) TDI TMS (Input)
VIH VIL 508 Input Data Valid 510 509
TDO (Output) 511 TDO (Output) 510 TDO (Output)
Output Data Valid
Output Data Valid AA0498
Figure 3-41 Test Access Port Timing Diagram
DSP56367 Technical Data, Rev. 2.1 3-54 Freescale Semiconductor
4
4.1
Packaging
Pin-out and Package Information
This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for the package. The DSP56367 is available in a 144-pin LQFP package. Table 4-1and Table 4-2 show the pin/name assignments for the packages.
4.1.1
LQFP Package Description
Top view of the 144-pin LQFP package is shown in Figure 4-1 with its pin-outs. The package drawing is shown in Figure 4-2.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 4-1
Pin-out and Package Information
SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS ADO ACI TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 38 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MISO/SDA MOSI/HA0 TMS TCK TDI TDO SDO4_1/SDI1_1 MODA/IRQA# MODB/IRQB# MODCIRQC# MODD/IRQD# D23 D22 D21 GNDD VCCD D20 GNDQ VCCQL D19 D18 D17 D16 D15 GNDD VCCD D14 D13 D12 D11 D10 D9 GNDD VCCD D8 D7
D6 D5 D4 D3 GNDD VCCD D2 D1 D0 A17 A16 A15 GNDA VCCQH A14 A13 A12 VCCQL GNDQ A11 A10 GNDA VCCA A9 A8 A7 A6 GNDA VCCA A5 A4 A3 A2 GNDA VCCA A1
4-2
HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 AA2 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# TA# BR# BB# VCCC GNDC WR# RD# AA1 AA0 BG# A0
Figure 4-1 144-pin package
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor
Pin-out and Package Information
Table 4-1 Signal Identification by Name
Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 AA0 AA1 AA2 ACI ADO BB# BG# BR# CAS# D0 D1 D2 D3 D4 D5 D6 D7 D8 Pin No. 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 70 69 51 28 27 64 71 63 52 100 101 102 105 106 107 108 109 110 Signal Name D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 EXTAL FSR FSR_1 FST FST_1 GNDA GNDA GNDA GNDA GNDC GNDC GNDD GNDD GNDD GNDD GNDH GNDP GNDQ GNDQ GNDQ GNDQ Pin No. 113 114 115 116 117 118 121 122 123 124 125 128 131 132 133 55 13 59 12 50 75 81 87 96 58 66 104 112 120 130 39 47 19 54 90 127 Signal Name GNDS GNDS HA8/HA1 HA9/HA2 HACK/HRRQ HAD0 HAD1 HAD2 HAD3 HAD4 HAD5 HAD6 HAD7 HAS/HA0 HCKR HCKT HCS/HA10 HDS/HWR HOREQ/HTRQ HREQ# HRW/HRD MODA/IRQA# MODB/IRQB# MODC/IRQC# MODD/IRQD# MISO/SDA MOSI/HA0 PCAP PINIT/NMI# RD# RESET# SCK/SCL SCKR SCKR_1 SCKT SCKT_1 Pin No. 9 26 32 31 23 43 42 41 40 37 36 35 34 33 17 16 30 21 24 3 22 137 136 135 134 144 143 46 61 68 44 1 15 60 14 53 Signal Name SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 SDO4/SDI1 SDO4_1/SDI1_1 SDO5/SDI0 SDO5_1/SDI0_1 SS#/HA2 TA# TCK TDI TDO TIO0 TMS VCCA VCCA VCCA VCCC VCCC VCCD VCCD VCCD VCCD VCCH VCCQH VCCQH VCCQH VCCQL VCCQL VCCQL VCCQL VCCP VCCS VCCS WR# Pin No. 4 5 6 7 10 138 11 48 2 62 141 140 139 29 142 74 80 86 57 65 103 111 119 129 38 20 95 49 18 56 91 126 45 8 25 67
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 4-3
Pin-out and Package Information
Table 4-2
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Signal Name SCK/SCL SS#/HA2 HREQ# SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 VCCS GNDS SDO4/SDI1 SDO5/SDI0 FST FSR SCKT SCKR HCKT HCKR VCCQL GNDQ VCCQH HDS/HWR HRW/HRD HACK/HRRQ HOREQ/HTRQ VCCS GNDS ADO ACI TIO0 HCS/HA10 HA9/HA2 HA8/HA1 HAS/HA0 HAD7 HAD6 HAD5 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Signal Identification by Pin Number
Signal Name HAD4 VCCH GNDH HAD3 HAD2 HAD1 HAD0 RESET# VCCP PCAP GNDP SDO5_1/SDI0_1 VCCQH FST_1 AA2 CAS# SCKT_1 GNDQ EXTAL VCCQL VCCC GNDC FSR_1 SCKR_1 PINIT/NMI# TA# BR# BB# VCCC GNDC WR# RD# AA1 AA0 BG# A0 Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Signal Name A1 VCCA GNDA A2 A3 A4 A5 VCCA GNDA A6 A7 A8 A9 VCCA GNDA A10 A11 GNDQ VCCQL A12 A13 A14 VCCQH GNDA A15 A16 A17 D0 D1 D2 VCCD GNDD D3 D4 D5 D6 Pin No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 D7 D8 VCCD GNDD D9 D10 D11 D12 D13 D14 VCCD GNDD D15 D16 D17 D18 D19 VCCQL GNDQ D20 VCCD GNDD D21 D22 D23 MODD/IRQD# MODC/IRQC# MODB/IRQB# MODA/IRQA# SDO4_1/SDI1_1 TDO TDI TCK TMS MOSI/HA0 MISO/SDA Signal Name
DSP56367 Technical Data, Rev. 2.1 4-4 Freescale Semiconductor
Pin-out and Package Information
4.1.2
LQFP Package Mechanical Drawing
Figure 4-2 DSP56367 144-pin LQFP Package (1 of 3)
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 4-5
Pin-out and Package Information
Figure 4-3 DSP56367 144-pin LQFP Package (2 of 3)
DSP56367 Technical Data, Rev. 2.1 4-6 Freescale Semiconductor
Pin-out and Package Information
Figure 4-4 DSP56367 144-pin LQFP Package (3 of 3)
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 4-7
Pin-out and Package Information
DSP56367 Technical Data, Rev. 2.1 4-8 Freescale Semiconductor
5
5.1
Design Considerations
Thermal Design Considerations
TJ = T A + ( P D x R JA )
An estimation of the chip junction temperature, TJ, in C can be obtained from the following equation:
Where: TA = ambient temperature C RqJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package W Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance. R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 5-1
Electrical Design Considerations
*
* *
To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation: (TJ - TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, thermal characterization parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
5.2
Electrical Design Considerations
CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields. However, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). The suggested value for a pull-up or pull-down resistor is 10 k ohm.
Use the following list of recommendations to assure correct DSP operation: * Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to each GND pin. * Use at least six 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. * Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 1.2 cm (0.5 inch) per capacitor lead. * Use at least a four-layer PCB with two inner layers for VCC and GND. * Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order of 15 cm (6 inches) are recommended.
DSP56367 Technical Data, Rev. 2.1 5-2 Freescale Semiconductor
Power Consumption Considerations
*
* * * * *
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except for the three pins with internal pull-up resistors (TMS, TDI, TCK). Take special care to minimize noise levels on the VCCP and GNDP pins. If multiple DSP56367 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of RESET. At power-up, ensure that the voltage difference between the 3.3 V tolerant pins and the chip VCC never exceeds a TBD voltage.
5.3
Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the following formula: I = CxVxf where: C V f = node/pin capacitance = voltage swing = frequency of node/pin toggle
Example 1. Power Consumption
For a Port A address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 100 MHz clock, toggling at its maximum possible rate (50 MHz), the current consumption is
I = 50 x 10
- 12
x 3.3 x 50 x 10 = 8.25mA
6
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption, do the following: * Set the EBD bit when not accessing external memory. * Minimize external memory accesses and use internal memory accesses. * Minimize the number of pins that are switching. * Minimize the capacitive load on the pins. * Connect the unused inputs to pull-up or pull-down resistors. * Disable unused peripherals.
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 5-3
PLL Performance Issues
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board effects (i.e., to compensate for measured board current not caused by the DSP). A benchmark power consumption test algorithm is listed in Appendix A, "Power Consumption Benchmark". Use the test algorithm, specific test current measurements, and the following equation to derive the current per MIPS value. I MIPS = I MHz = ( I typF2 - I typF1 ) ( F2 - F1 ) where: ItypF2 = current at F2 ItypF1 = current at F1 F2 F1 = high frequency (any specified operating frequency) = low frequency (any specified operating frequency lower than F2) NOTE F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be 33 MHz. The degree of difference between F1 and F2 determines the amount of precision with which the current rating can be determined for an application.
5.4
PLL Performance Issues
The following explanations should be considered as general observations on expected PLL behavior. There is no testing that verifies these exact numbers. These observations were measured on a limited number of parts and were not verified over the entire temperature and voltage ranges.
5.4.1
Input (EXTAL) Jitter Requirements
The allowed jitter on the frequency of EXTAL is 0.5%. If the rate of change of the frequency of EXTAL is slow (i.e., it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e., it does not stay at an extreme value for a long time), then the allowed jitter can be 2%. The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values.
DSP56367 Technical Data, Rev. 2.1 5-4 Freescale Semiconductor
Appendix A Power Consumption Benchmark
The following benchmark program permits evaluation of DSP power usage in a test situation. It enables the PLL, disables the external clock, and uses repeated multiply-accumulate instructions with a set of synthetic DSP application data to emulate intensive sustained DSP operation.
;***********************************;******************************** ;* ;* CHECKS Typical Power Consumption
;******************************************************************** page 200,55,0,0,0 nolist I_VEC EQU START EQU INT_PROG INT_XDAT INT_YDAT $000000 $8000 EQU $100 EQU $0 EQU $0 ; ; ; ; ; Interrupt vectors for program debug only MAIN (external) program starting address INTERNAL program memory starting address INTERNAL X-data memory starting address INTERNAL Y-data memory starting address
INCLUDE "ioequ.asm" INCLUDE "intequ.asm" list org ; movep #$0123FF,x:M_BCR; BCR: Area 3 : 1 w.s (SRAM) ; Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; XTAL disable ; PLL enable ; CLKOUT disable ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor A-1
P:START
do move move XLOAD_LOOP ; ; Load the Y-data ; move move do move move YLOAD_LOOP ; jmp PROG_START move move move move ; clr clr move move move move bset ; sbr dor mac mac add mac mac move bra nop nop nop nop PROG_END nop nop
#(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+
#INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+
INT_PROG
#$0,r0 #$0,r4 #$3f,m0 #$3f,m4 a b #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr #60,_end x0,y0,a x1,y1,a a,b x0,y0,a x1,y1,a b1,x:$ff sbr
; ebd
x:(r0)+,x1 x:(r0)+,x0 x:(r0)+,x1
y:(r4)+,y1 y:(r4)+,y0
y:(r4)+,y0
_end
XDAT_START ; org dc dc dc dc
x:0 $262EB9 $86F2FE $E56A5F $616CAC
DSP56367 Technical Data, Rev. 2.1 A-2 Freescale Semiconductor
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$8FFD75 $9210A $A06D7B $CEA798 $8DFBF1 $A063D6 $6C6657 $C2A544 $A3662D $A4E762 $84F0F3 $E6F1B0 $B3829 $8BF7AE $63A94F $EF78DC $242DE5 $A3E0BA $EBAB6B $8726C8 $CA361 $2F6E86 $A57347 $4BE774 $8F349D $A1ED12 $4BFCE3 $EA26E0 $CD7D99 $4BA85E $27A43F $A8B10C $D3A55 $25EC6A $2A255B $A5F1F8 $2426D1 $AE6536 $CBBC37 $6235A4 $37F0D $63BEC2 $A5E4D3 $8CE810 $3FF09 $60E50E $CFFB2F $40753C $8262C5 $CA641A $EB3B4B $2DA928 $AB6641 $28A7E6 $4E2127
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor A-3
dc dc dc dc dc XDAT_END YDAT_START ; org dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc
$482FD4 $7257D $E53C72 $1A8C3 $E27540
y:0 $5B6DA $C3F70B $6A39E8 $81E801 $C666A6 $46F8E7 $AAEC94 $24233D $802732 $2E3C83 $A43E00 $C2B639 $85A47E $ABFDDF $F3A2C $2D7CF5 $E16A8A $ECB8FB $4BED18 $43F371 $83A556 $E1E9D7 $ACA2C4 $8135AD $2CE0E2 $8F2C73 $432730 $A87FA9 $4A292E $A63CCF $6BA65C $E06D65 $1AA3A $A1B6EB $48AC48 $EF7AE1 $6E3006 $62F6C7 $6064F4 $87E41D $CB2692 $2C3863 $C6BC60 $43A519 $6139DE $ADF7BF
DSP56367 Technical Data, Rev. 2.1 A-4 Freescale Semiconductor
dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc dc YDAT_END
$4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor A-5
NOTES
DSP56367 Technical Data, Rev. 2.1 A-6 Freescale Semiconductor
Index
A
ac electrical characteristics 4 wait states selection guide 21 write access 28 out of page and refresh timings 11 wait states 23 15 wait states 25 4 wait states 21 Page mode read accesses 20 wait states selection guide 15 write accesses 19 Page mode timings 3 wait states 16 4 wait states 17 refresh access 29 DSP56300 Family Manual 3
B
Boundary Scan (JTAG Port) timing diagram 53 bus external address 4 external data 4
C
Clock 4 clock external 4 operation 5 clocks internal 4
E
electrical design considerations 3 Enhanced Serial Audio Interface 13, 16 ESAI 13, 16 receiver timing 49, 50 timings 45 transmitter timing 48 EXTAL jitter 4 external address bus 4 external bus control 4, 5, 6 external clock operation 4 external data bus 4 external interrupt timing (negative edge-triggered) 11 external level-sensitive fast interrupt timing 10 external memory access (DMA Source) timing 12 External Memory Expansion Port 4, 12
D
DAX 18 dc electrical characteristics 3 design considerations electrical 3 PLL 4 power consumption 3 thermal 1 Digital Audio Transmitter 18 DRAM out of page
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor Index-1
F
functional signal groups 1
M
maximum ratings 1, 2 mode control 6, 7 Mode select timing 7 multiplexed bus timings read 35 write 36
G
GPIO 18 GPIO timing 51 Ground 3
N
non-multiplexed bus timings read 33 write 34
H
HDI08 8, 10 HDI08 timing 31 Host Interface 8, 10 Host Interface timing 31
O
OnCE module 19 operating mode select timing 11
I
internal clocks 4 interrupt and mode control 6, 7 interrupt control 6, 7 interrupt timing 7 external level-sensitive fast 10 external negative edge-triggered 11
P
package TQFP description 1, 4 Phase Lock Loop 6 PLL 4, 6 Characteristics 6 performance issues 4 PLL design considerations 4 PLL performance issues 4 Port A 4 Port B 9, 10 Port C 13, 16 Port D 18 Power 2 power consumption design considerations 3
J
Jitter 4 JTAG 19 JTAG Port timing 52, 53
DSP56367 Technical Data, Rev. 2.1 Index-2 Freescale Semiconductor
R
recovery from Stop state using IRQA 11, 12 RESET 7 Reset timing 7, 10
interrupt 7 mode select 7 Reset 7 Stop 7 TQFP pin list by number 4 pin-out drawing (top) 1
S
Serial Host Interface 11 SHI 11 signal groupings 1 signals 1 SRAM read and write accesses 12 write access 14 Stop state recovery from 11, 12 Stop timing 7 supply voltage 2
T
Test Access Port timing diagram 54 Test Clock (TCLK) input timing diagram 53 thermal characteristics 2 thermal design considerations 1 Timer 18 event input restrictions 51 timing 51 Timing Digital Audio Transmitter (DAX) 50 Enhanced Serial Audio Interface (ESAI) 48 General Purpose I/O (GPIO) Timing 45 OnCETM (On Chip Emulator) Timing 45 Serial Host Interface (SHI) SPI Protocol Timing 37 Serial Host Interface (SHI) Timing 37 timing
DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor Index-3
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Document Number: DSP56367 Rev. 2.1 1/2007

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